Amanda Lee Bailey

Array ( [id] => 8267280 [patent_doc_number] => 20120166707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Data management in flash memory using probability of charge disturbances' [patent_app_type] => utility [patent_app_number] => 12/930013 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12930013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8714662 [patent_doc_number] => 08400806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/972238 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 55 [patent_no_of_words] => 24376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12972238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8877286 [patent_doc_number] => 08472260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Semiconductor memory apparatus and method for discharging wordline thereof' [patent_app_type] => utility [patent_app_number] => 12/963341 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4897 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8539371 [patent_doc_number] => 08315094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/957865 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5821 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12957865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6117740 [patent_doc_number] => 20110075466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY' [patent_app_type] => utility [patent_app_number] => 12/955377 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4618 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20110075466.pdf [firstpage_image] =>[orig_patent_app_number] => 12955377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8179890 [patent_doc_number] => 08179716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Non-volatile programmable logic gates and adders' [patent_app_type] => utility [patent_app_number] => 12/953544 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 6459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/179/08179716.pdf [firstpage_image] =>[orig_patent_app_number] => 12953544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6140570 [patent_doc_number] => 20110128806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT TEST METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/949063 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9830 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128806.pdf [firstpage_image] =>[orig_patent_app_number] => 12949063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6006063 [patent_doc_number] => 20110058425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'Integrated Flash Memory Systems And Methods For Load Compensation' [patent_app_type] => utility [patent_app_number] => 12/947719 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8052 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20110058425.pdf [firstpage_image] =>[orig_patent_app_number] => 12947719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8019833 [patent_doc_number] => 08139425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Voltage regulation method and memory applying thereof' [patent_app_type] => utility [patent_app_number] => 12/943372 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3149 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/139/08139425.pdf [firstpage_image] =>[orig_patent_app_number] => 12943372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6073498 [patent_doc_number] => 20110047325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND SIGNAL PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/938079 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4048 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047325.pdf [firstpage_image] =>[orig_patent_app_number] => 12938079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8157056 [patent_doc_number] => 20120099359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Nonvolatile Memory Architecture' [patent_app_type] => utility [patent_app_number] => 12/911603 [patent_app_country] => US [patent_app_date] => 2010-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10621 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20120099359.pdf [firstpage_image] =>[orig_patent_app_number] => 12911603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5983252 [patent_doc_number] => 20110096609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'Novel punch-through free program scheme for nt-string flash design' [patent_app_type] => utility [patent_app_number] => 12/925489 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 29046 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20110096609.pdf [firstpage_image] =>[orig_patent_app_number] => 12925489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8125265 [patent_doc_number] => 20120087180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT FOR LOW AND HIGH VOLTAGE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/901845 [patent_app_country] => US [patent_app_date] => 2010-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20120087180.pdf [firstpage_image] =>[orig_patent_app_number] => 12901845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6123490 [patent_doc_number] => 20110085404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'Semiconductor memory device and information processing system including the same' [patent_app_type] => utility [patent_app_number] => 12/923751 [patent_app_country] => US [patent_app_date] => 2010-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11638 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085404.pdf [firstpage_image] =>[orig_patent_app_number] => 12923751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6147772 [patent_doc_number] => 20110019455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'LOW COST HIGH DENSITY RECTIFIER MATRIX MEMORY' [patent_app_type] => utility [patent_app_number] => 12/898205 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2951 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20110019455.pdf [firstpage_image] =>[orig_patent_app_number] => 12898205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8092671 [patent_doc_number] => 20120081945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'MEMORY ARRAY WITH GRADED RESISTANCE LINES' [patent_app_type] => utility [patent_app_number] => 12/896641 [patent_app_country] => US [patent_app_date] => 2010-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3482 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20120081945.pdf [firstpage_image] =>[orig_patent_app_number] => 12896641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9141877 [patent_doc_number] => 08582351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability' [patent_app_type] => utility [patent_app_number] => 12/892191 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5384 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12892191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5991797 [patent_doc_number] => 20110013450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'METHOD FOR ADAPTIVE SETTING OF STATE VOLTAGE LEVELS IN NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/890267 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11511 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20110013450.pdf [firstpage_image] =>[orig_patent_app_number] => 12890267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4645713 [patent_doc_number] => 08023324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Memory controller self-calibration for removing systemic influence' [patent_app_type] => utility [patent_app_number] => 12/889461 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/023/08023324.pdf [firstpage_image] =>[orig_patent_app_number] => 12889461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7708834 [patent_doc_number] => 20120002462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'RESISTANCE-CHANGE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/887409 [patent_app_country] => US [patent_app_date] => 2010-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 11698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12887409 [rel_patent_id] =>[rel_patent_doc_number] =>)