Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4625618 [patent_doc_number] => 08004924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Voltage regulator for memory' [patent_app_type] => utility [patent_app_number] => 12/388257 [patent_app_country] => US [patent_app_date] => 2009-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004924.pdf [firstpage_image] =>[orig_patent_app_number] => 12388257 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/388257
Voltage regulator for memory Feb 17, 2009 Issued
Array ( [id] => 8179886 [patent_doc_number] => 08179708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Anti-cross-talk circuitry for ROM arrays' [patent_app_type] => utility [patent_app_number] => 12/388293 [patent_app_country] => US [patent_app_date] => 2009-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3480 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/179/08179708.pdf [firstpage_image] =>[orig_patent_app_number] => 12388293 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/388293
Anti-cross-talk circuitry for ROM arrays Feb 17, 2009 Issued
Array ( [id] => 6484109 [patent_doc_number] => 20100208540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'INTEGRATED CIRCUIT WITH MULTIPORTED MEMORY SUPERCELL AND DATA PATH SWITCHING CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 12/371363 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4955 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20100208540.pdf [firstpage_image] =>[orig_patent_app_number] => 12371363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/371363
Integrated circuit with multiported memory supercell and data path switching circuitry Feb 12, 2009 Issued
Array ( [id] => 4482150 [patent_doc_number] => 07907436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Nonvolatile semiconductor storage device and data writing method therefor' [patent_app_type] => utility [patent_app_number] => 12/370111 [patent_app_country] => US [patent_app_date] => 2009-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/907/07907436.pdf [firstpage_image] =>[orig_patent_app_number] => 12370111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/370111
Nonvolatile semiconductor storage device and data writing method therefor Feb 11, 2009 Issued
Array ( [id] => 5301796 [patent_doc_number] => 20090296448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'DIODE AS VOLTAGE DOWN CONVERTER FOR OTP HIGH PROGRAMMING VOLTAGE APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/367455 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20090296448.pdf [firstpage_image] =>[orig_patent_app_number] => 12367455 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/367455
DIODE AS VOLTAGE DOWN CONVERTER FOR OTP HIGH PROGRAMMING VOLTAGE APPLICATIONS Feb 5, 2009 Abandoned
Array ( [id] => 6316617 [patent_doc_number] => 20100195419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Configurable Write Policy in a Memory System' [patent_app_type] => utility [patent_app_number] => 12/365019 [patent_app_country] => US [patent_app_date] => 2009-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4805 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195419.pdf [firstpage_image] =>[orig_patent_app_number] => 12365019 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/365019
Configurable write policy in a memory system Feb 2, 2009 Issued
Array ( [id] => 4474541 [patent_doc_number] => 07944729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array' [patent_app_type] => utility [patent_app_number] => 12/360931 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944729.pdf [firstpage_image] =>[orig_patent_app_number] => 12360931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/360931
Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array Jan 27, 2009 Issued
Array ( [id] => 5354090 [patent_doc_number] => 20090185434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'OPERATIONAL MODE CONTROL IN SERIAL-CONNECTED MEMORY BASED ON IDENTIFIER' [patent_app_type] => utility [patent_app_number] => 12/352009 [patent_app_country] => US [patent_app_date] => 2009-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5760 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20090185434.pdf [firstpage_image] =>[orig_patent_app_number] => 12352009 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352009
Operational mode control in serial-connected memory based on identifier Jan 11, 2009 Issued
Array ( [id] => 4581850 [patent_doc_number] => 07859917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Voltage regulation method and memory applying thereof' [patent_app_type] => utility [patent_app_number] => 12/350381 [patent_app_country] => US [patent_app_date] => 2009-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859917.pdf [firstpage_image] =>[orig_patent_app_number] => 12350381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/350381
Voltage regulation method and memory applying thereof Jan 7, 2009 Issued
Array ( [id] => 8556672 [patent_doc_number] => 08331150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Integrated SRAM and FLOTOX EEPROM memory device' [patent_app_type] => utility [patent_app_number] => 12/319241 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 11278 [patent_no_of_claims] => 90 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12319241 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/319241
Integrated SRAM and FLOTOX EEPROM memory device Jan 4, 2009 Issued
Array ( [id] => 4559676 [patent_doc_number] => 07961505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Electronic device, method of manufacturing the same, and storage device' [patent_app_type] => utility [patent_app_number] => 12/348509 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 16098 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961505.pdf [firstpage_image] =>[orig_patent_app_number] => 12348509 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/348509
Electronic device, method of manufacturing the same, and storage device Jan 4, 2009 Issued
Array ( [id] => 6361490 [patent_doc_number] => 20100074031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'TEST MODE SIGNAL GENERATOR FOR SEMICONDUCTOR MEMORY AND METHOD OF GENERATING TEST MODE SIGNALS' [patent_app_type] => utility [patent_app_number] => 12/345889 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9132 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20100074031.pdf [firstpage_image] =>[orig_patent_app_number] => 12345889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345889
Test mode signal generator for semiconductor memory and method of generating test mode signals Dec 29, 2008 Issued
Array ( [id] => 4598607 [patent_doc_number] => 07983095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/345835 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8448 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/983/07983095.pdf [firstpage_image] =>[orig_patent_app_number] => 12345835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345835
Semiconductor memory apparatus Dec 29, 2008 Issued
Array ( [id] => 4590400 [patent_doc_number] => 07852661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Write-assist SRAM cell' [patent_app_type] => utility [patent_app_number] => 12/345263 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3583 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/852/07852661.pdf [firstpage_image] =>[orig_patent_app_number] => 12345263 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345263
Write-assist SRAM cell Dec 28, 2008 Issued
Array ( [id] => 5433995 [patent_doc_number] => 20090168581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/344379 [patent_app_country] => US [patent_app_date] => 2008-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3858 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168581.pdf [firstpage_image] =>[orig_patent_app_number] => 12344379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344379
Fuse monitoring circuit for semiconductor memory device Dec 25, 2008 Issued
Array ( [id] => 154440 [patent_doc_number] => 07679959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages' [patent_app_type] => utility [patent_app_number] => 12/276957 [patent_app_country] => US [patent_app_date] => 2008-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 10051 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679959.pdf [firstpage_image] =>[orig_patent_app_number] => 12276957 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/276957
Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages Nov 23, 2008 Issued
Array ( [id] => 244280 [patent_doc_number] => 07590019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Low voltage data path and current sense amplifier' [patent_app_type] => utility [patent_app_number] => 12/274570 [patent_app_country] => US [patent_app_date] => 2008-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590019.pdf [firstpage_image] =>[orig_patent_app_number] => 12274570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/274570
Low voltage data path and current sense amplifier Nov 19, 2008 Issued
Array ( [id] => 7754070 [patent_doc_number] => 08111542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => '8T low leakage SRAM cell' [patent_app_type] => utility [patent_app_number] => 12/273959 [patent_app_country] => US [patent_app_date] => 2008-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2054 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/111/08111542.pdf [firstpage_image] =>[orig_patent_app_number] => 12273959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/273959
8T low leakage SRAM cell Nov 18, 2008 Issued
Array ( [id] => 5451187 [patent_doc_number] => 20090067223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL' [patent_app_type] => utility [patent_app_number] => 12/265042 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4779 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20090067223.pdf [firstpage_image] =>[orig_patent_app_number] => 12265042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265042
Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell Nov 4, 2008 Issued
Array ( [id] => 5321687 [patent_doc_number] => 20090059677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/260124 [patent_app_country] => US [patent_app_date] => 2008-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 23469 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059677.pdf [firstpage_image] =>[orig_patent_app_number] => 12260124 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/260124
Semiconductor device Oct 28, 2008 Issued
Menu