Amanda Lee Bailey

Array ( [id] => 7536443 [patent_doc_number] => 08050082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Two-stage 8T SRAM cell design' [patent_app_type] => utility [patent_app_number] => 12/259009 [patent_app_country] => US [patent_app_date] => 2008-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3160 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/050/08050082.pdf [firstpage_image] =>[orig_patent_app_number] => 12259009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5321706 [patent_doc_number] => 20090059696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Multi-port memory device' [patent_app_type] => utility [patent_app_number] => 12/288878 [patent_app_country] => US [patent_app_date] => 2008-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5526 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059696.pdf [firstpage_image] =>[orig_patent_app_number] => 12288878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7999357 [patent_doc_number] => 08081526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Serialized chip enables' [patent_app_type] => utility [patent_app_number] => 12/238935 [patent_app_country] => US [patent_app_date] => 2008-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4015 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/081/08081526.pdf [firstpage_image] =>[orig_patent_app_number] => 12238935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5277030 [patent_doc_number] => 20090129162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure' [patent_app_type] => utility [patent_app_number] => 12/284890 [patent_app_country] => US [patent_app_date] => 2008-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4339 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20090129162.pdf [firstpage_image] =>[orig_patent_app_number] => 12284890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4452849 [patent_doc_number] => 07965539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Nonvolatile memory element, nonvolatile semiconductor memory apparatus, and reading method and writing method therefor' [patent_app_type] => utility [patent_app_number] => 12/516703 [patent_app_country] => US [patent_app_date] => 2008-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 13041 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965539.pdf [firstpage_image] =>[orig_patent_app_number] => 12516703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4581640 [patent_doc_number] => 07859890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Memory device with multiple capacitor types' [patent_app_type] => utility [patent_app_number] => 12/200041 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 3468 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859890.pdf [firstpage_image] =>[orig_patent_app_number] => 12200041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8026167 [patent_doc_number] => 08142159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Fan and motor thereof' [patent_app_type] => utility [patent_app_number] => 12/191708 [patent_app_country] => US [patent_app_date] => 2008-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4189 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/142/08142159.pdf [firstpage_image] =>[orig_patent_app_number] => 12191708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4758001 [patent_doc_number] => 20080310227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND RELATED PROGRAMMING METHOD' [patent_app_type] => utility [patent_app_number] => 12/190215 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4549 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20080310227.pdf [firstpage_image] =>[orig_patent_app_number] => 12190215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5520725 [patent_doc_number] => 20090028706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Vertical Axle Helix Monoblock Wind Turbine' [patent_app_type] => utility [patent_app_number] => 12/177889 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 789 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20090028706.pdf [firstpage_image] =>[orig_patent_app_number] => 12177889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 264769 [patent_doc_number] => 07570540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Multiport semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/219350 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 9064 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570540.pdf [firstpage_image] =>[orig_patent_app_number] => 12219350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4503833 [patent_doc_number] => 07948799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Structure and method of sub-gate NAND memory with bandgap engineered SONOS devices' [patent_app_type] => utility [patent_app_number] => 12/175297 [patent_app_country] => US [patent_app_date] => 2008-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 62 [patent_no_of_words] => 15474 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948799.pdf [firstpage_image] =>[orig_patent_app_number] => 12175297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7969935 [patent_doc_number] => 07940542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Semiconductor device having multiport memory' [patent_app_type] => utility [patent_app_number] => 12/144051 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 11900 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940542.pdf [firstpage_image] =>[orig_patent_app_number] => 12144051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7743610 [patent_doc_number] => 08107312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Memory chip array' [patent_app_type] => utility [patent_app_number] => 12/213121 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2460 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/107/08107312.pdf [firstpage_image] =>[orig_patent_app_number] => 12213121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8537583 [patent_doc_number] => 08313300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Rotor for centrifugal compressor' [patent_app_type] => utility [patent_app_number] => 12/156941 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4658 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12156941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4559960 [patent_doc_number] => 07961533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Method and apparatus for implementing write levelization in memory subsystems' [patent_app_type] => utility [patent_app_number] => 12/127059 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961533.pdf [firstpage_image] =>[orig_patent_app_number] => 12127059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4584532 [patent_doc_number] => 07826267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array' [patent_app_type] => utility [patent_app_number] => 12/126853 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2760 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826267.pdf [firstpage_image] =>[orig_patent_app_number] => 12126853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5489197 [patent_doc_number] => 20090290268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'NONVOLATILE PROGRAMMABLE LOGIC GATES AND ADDERS' [patent_app_type] => utility [patent_app_number] => 12/125975 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6412 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20090290268.pdf [firstpage_image] =>[orig_patent_app_number] => 12125975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5489366 [patent_doc_number] => 20090290437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'CIRCUIT FOR AND AN ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/126069 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20090290437.pdf [firstpage_image] =>[orig_patent_app_number] => 12126069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 114190 [patent_doc_number] => 07719902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage' [patent_app_type] => utility [patent_app_number] => 12/126375 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 13042 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719902.pdf [firstpage_image] =>[orig_patent_app_number] => 12126375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5489368 [patent_doc_number] => 20090290439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'HIGH PERFORMANCE METAL GATE POLYGATE 8 TRANSISTOR SRAM CELL WITH REDUCED VARIABILITY' [patent_app_type] => utility [patent_app_number] => 12/125637 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5299 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20090290439.pdf [firstpage_image] =>[orig_patent_app_number] => 12125637 [rel_patent_id] =>[rel_patent_doc_number] =>)