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Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 46522 [patent_doc_number] => 07778073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Integrated circuit having NAND memory cell strings' [patent_app_type] => utility [patent_app_number] => 11/872655 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 18127 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/778/07778073.pdf [firstpage_image] =>[orig_patent_app_number] => 11872655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/872655
Integrated circuit having NAND memory cell strings Oct 14, 2007 Issued
Array ( [id] => 76585 [patent_doc_number] => 07751245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Programming sequence in NAND memory' [patent_app_type] => utility [patent_app_number] => 11/973677 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8546 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/751/07751245.pdf [firstpage_image] =>[orig_patent_app_number] => 11973677 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/973677
Programming sequence in NAND memory Oct 9, 2007 Issued
Array ( [id] => 4725606 [patent_doc_number] => 20080205147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Local self-boost inhibit scheme with shielded word line' [patent_app_type] => utility [patent_app_number] => 11/973733 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9016 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205147.pdf [firstpage_image] =>[orig_patent_app_number] => 11973733 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/973733
Local self-boost inhibit scheme with shielded word line Oct 9, 2007 Issued
Array ( [id] => 297066 [patent_doc_number] => 07542343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-02 [patent_title] => 'Planar NAND flash memory' [patent_app_type] => utility [patent_app_number] => 11/858895 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 10138 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/542/07542343.pdf [firstpage_image] =>[orig_patent_app_number] => 11858895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858895
Planar NAND flash memory Sep 20, 2007 Issued
Array ( [id] => 596626 [patent_doc_number] => 07440328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Operation methods for a non-volatile memory cell in an array' [patent_app_type] => utility [patent_app_number] => 11/856457 [patent_app_country] => US [patent_app_date] => 2007-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3387 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440328.pdf [firstpage_image] =>[orig_patent_app_number] => 11856457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/856457
Operation methods for a non-volatile memory cell in an array Sep 16, 2007 Issued
Array ( [id] => 6596 [patent_doc_number] => 07817467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Memory controller self-calibration for removing systemic influence' [patent_app_type] => utility [patent_app_number] => 11/851439 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7663 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/817/07817467.pdf [firstpage_image] =>[orig_patent_app_number] => 11851439 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851439
Memory controller self-calibration for removing systemic influence Sep 6, 2007 Issued
Array ( [id] => 4897326 [patent_doc_number] => 20080116939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'SEMICONDUCTOR DEVICE, LOGIC CIRCUIT AND ELECTRONIC EQUIPMENT' [patent_app_type] => utility [patent_app_number] => 11/851861 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7192 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116939.pdf [firstpage_image] =>[orig_patent_app_number] => 11851861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851861
Semiconductor device, logic circuit and electronic equipment Sep 6, 2007 Issued
Array ( [id] => 5321708 [patent_doc_number] => 20090059698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'METHOD FOR TESTING MEMORY' [patent_app_type] => utility [patent_app_number] => 11/850061 [patent_app_country] => US [patent_app_date] => 2007-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2101 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059698.pdf [firstpage_image] =>[orig_patent_app_number] => 11850061 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850061
Method for testing memory Sep 4, 2007 Issued
Array ( [id] => 212486 [patent_doc_number] => 07623398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Semiconductor memory device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/849379 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10579 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/623/07623398.pdf [firstpage_image] =>[orig_patent_app_number] => 11849379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849379
Semiconductor memory device and semiconductor device Sep 3, 2007 Issued
Array ( [id] => 7598921 [patent_doc_number] => 07583528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Magnetic memory device, method for writing into magnetic memory device and method for reading magnetic memory device' [patent_app_type] => utility [patent_app_number] => 11/848571 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 8593 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/583/07583528.pdf [firstpage_image] =>[orig_patent_app_number] => 11848571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848571
Magnetic memory device, method for writing into magnetic memory device and method for reading magnetic memory device Aug 30, 2007 Issued
Array ( [id] => 4774160 [patent_doc_number] => 20080059822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Memory system for controlling power and method thereof' [patent_app_type] => utility [patent_app_number] => 11/896123 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059822.pdf [firstpage_image] =>[orig_patent_app_number] => 11896123 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896123
Memory system for controlling power and method thereof Aug 28, 2007 Issued
Array ( [id] => 308461 [patent_doc_number] => 07532539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to load' [patent_app_type] => utility [patent_app_number] => 11/833485 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/532/07532539.pdf [firstpage_image] =>[orig_patent_app_number] => 11833485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833485
Semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to load Aug 2, 2007 Issued
Array ( [id] => 5359558 [patent_doc_number] => 20090034352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'METHOD AND CIRCUIT FOR PREVENTING HIGH VOLTAGE MEMORY DISTURB' [patent_app_type] => utility [patent_app_number] => 11/833545 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20090034352.pdf [firstpage_image] =>[orig_patent_app_number] => 11833545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833545
Method and circuit for preventing high voltage memory disturb Aug 2, 2007 Issued
Array ( [id] => 4804825 [patent_doc_number] => 20080016414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Low Cost High Density Rectifier Matrix Memory' [patent_app_type] => utility [patent_app_number] => 11/780909 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2925 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016414.pdf [firstpage_image] =>[orig_patent_app_number] => 11780909 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780909
Low cost high density rectifier matrix memory Jul 19, 2007 Issued
Array ( [id] => 240524 [patent_doc_number] => 07593246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Low cost high density rectifier matrix memory' [patent_app_type] => utility [patent_app_number] => 11/780916 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2933 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/593/07593246.pdf [firstpage_image] =>[orig_patent_app_number] => 11780916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780916
Low cost high density rectifier matrix memory Jul 19, 2007 Issued
Array ( [id] => 4942953 [patent_doc_number] => 20080080278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE INCLUDING WRITE DRIVER CONTROL CIRCUIT AND WRITE DRIVER CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 11/775313 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7278 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080278.pdf [firstpage_image] =>[orig_patent_app_number] => 11775313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775313
Semiconductor memory device including write driver control circuit and write driver control method Jul 9, 2007 Issued
Array ( [id] => 4686881 [patent_doc_number] => 20080031062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DETECTING BRIDGE DEFECTS AND BRIDGE DEFECT DETECTING METHOD PERFORMED IN THE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/775513 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2744 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20080031062.pdf [firstpage_image] =>[orig_patent_app_number] => 11775513 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775513
Semiconductor memory device capable of detecting bridge defects and bridge defect detecting method performed in the semiconductor memory device Jul 9, 2007 Issued
Array ( [id] => 204569 [patent_doc_number] => 07633785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Semiconductor memory device and method of generating chip enable signal thereof' [patent_app_type] => utility [patent_app_number] => 11/775245 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10025 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633785.pdf [firstpage_image] =>[orig_patent_app_number] => 11775245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775245
Semiconductor memory device and method of generating chip enable signal thereof Jul 9, 2007 Issued
Array ( [id] => 105316 [patent_doc_number] => 07724602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Memory controller with programmable regression model for power control' [patent_app_type] => utility [patent_app_number] => 11/775517 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724602.pdf [firstpage_image] =>[orig_patent_app_number] => 11775517 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775517
Memory controller with programmable regression model for power control Jul 9, 2007 Issued
Array ( [id] => 7590403 [patent_doc_number] => 07663958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/773779 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6784 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663958.pdf [firstpage_image] =>[orig_patent_app_number] => 11773779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773779
Semiconductor device Jul 4, 2007 Issued
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