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Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 85774 [patent_doc_number] => 07742329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory' [patent_app_type] => utility [patent_app_number] => 11/770839 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4170 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/742/07742329.pdf [firstpage_image] =>[orig_patent_app_number] => 11770839 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770839
Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory Jun 28, 2007 Issued
Array ( [id] => 4725595 [patent_doc_number] => 20080205136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'READ METHOD OF MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/771963 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3923 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205136.pdf [firstpage_image] =>[orig_patent_app_number] => 11771963 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771963
Read method of memory device Jun 28, 2007 Issued
Array ( [id] => 4696860 [patent_doc_number] => 20080219044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Read Disturb Reduction Circuit for Spin Transfer Torque Magnetoresistive Random Access Memory' [patent_app_type] => utility [patent_app_number] => 11/771065 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3909 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20080219044.pdf [firstpage_image] =>[orig_patent_app_number] => 11771065 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771065
Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory Jun 28, 2007 Issued
Array ( [id] => 4763876 [patent_doc_number] => 20080175087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'CIRCUIT FOR GENERATING A REFERENCE VOLTAGE' [patent_app_type] => utility [patent_app_number] => 11/771817 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2831 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175087.pdf [firstpage_image] =>[orig_patent_app_number] => 11771817 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771817
Circuit for generating a reference voltage Jun 28, 2007 Issued
Array ( [id] => 5200738 [patent_doc_number] => 20070300056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Non-Volatile Semiconductor Memory Device' [patent_app_type] => utility [patent_app_number] => 11/769404 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5365 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300056.pdf [firstpage_image] =>[orig_patent_app_number] => 11769404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769404
Non-volatile semiconductor memory device Jun 26, 2007 Issued
Array ( [id] => 297067 [patent_doc_number] => 07542344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Non-volatile memory device and self-compensation method thereof' [patent_app_type] => utility [patent_app_number] => 11/769313 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3877 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/542/07542344.pdf [firstpage_image] =>[orig_patent_app_number] => 11769313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769313
Non-volatile memory device and self-compensation method thereof Jun 26, 2007 Issued
Array ( [id] => 5209378 [patent_doc_number] => 20070247962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Semiconductor integrated circuit device, data processing system and memory system' [patent_app_type] => utility [patent_app_number] => 11/819085 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14147 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247962.pdf [firstpage_image] =>[orig_patent_app_number] => 11819085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819085
Semiconductor integrated circuit device, data processing system and memory system Jun 24, 2007 Abandoned
Array ( [id] => 5224011 [patent_doc_number] => 20070253277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Semiconductor integrated circuit device, data processing system and memory system' [patent_app_type] => utility [patent_app_number] => 11/819086 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14147 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253277.pdf [firstpage_image] =>[orig_patent_app_number] => 11819086 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819086
Semiconductor integrated circuit device, data processing system and memory system Jun 24, 2007 Abandoned
Array ( [id] => 5197944 [patent_doc_number] => 20070297262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING STACKED GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/765749 [patent_app_country] => US [patent_app_date] => 2007-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6195 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20070297262.pdf [firstpage_image] =>[orig_patent_app_number] => 11765749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765749
Semiconductor memory device having stacked gate including charge accumulation layer and control gate and test method thereof Jun 19, 2007 Issued
Array ( [id] => 4758020 [patent_doc_number] => 20080310246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/761655 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6996 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20080310246.pdf [firstpage_image] =>[orig_patent_app_number] => 11761655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/761655
Programmable pulsewidth and delay generating circuit for integrated circuits Jun 11, 2007 Issued
Array ( [id] => 578709 [patent_doc_number] => 07466619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/760959 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5544 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/466/07466619.pdf [firstpage_image] =>[orig_patent_app_number] => 11760959 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760959
Semiconductor memory device Jun 10, 2007 Issued
Array ( [id] => 275311 [patent_doc_number] => 07561481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Memory controllers and pad sequence control methods thereof' [patent_app_type] => utility [patent_app_number] => 11/760955 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 3539 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/561/07561481.pdf [firstpage_image] =>[orig_patent_app_number] => 11760955 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760955
Memory controllers and pad sequence control methods thereof Jun 10, 2007 Issued
Array ( [id] => 297087 [patent_doc_number] => 07542364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/760831 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/542/07542364.pdf [firstpage_image] =>[orig_patent_app_number] => 11760831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760831
Semiconductor memory device Jun 10, 2007 Issued
Array ( [id] => 5197920 [patent_doc_number] => 20070297238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'VOLTAGE REGULATOR FOR FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/760829 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20070297238.pdf [firstpage_image] =>[orig_patent_app_number] => 11760829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760829
Voltage regulator for flash memory device Jun 10, 2007 Issued
Array ( [id] => 4709631 [patent_doc_number] => 20080298157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'MULTI-DIE PACKAGED DEVICE' [patent_app_type] => utility [patent_app_number] => 11/760769 [patent_app_country] => US [patent_app_date] => 2007-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2985 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20080298157.pdf [firstpage_image] =>[orig_patent_app_number] => 11760769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760769
Multi-die packaged device Jun 9, 2007 Issued
Array ( [id] => 114189 [patent_doc_number] => 07719901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Solid state memory utilizing analog communication of data values' [patent_app_type] => utility [patent_app_number] => 11/758307 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6456 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719901.pdf [firstpage_image] =>[orig_patent_app_number] => 11758307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758307
Solid state memory utilizing analog communication of data values Jun 4, 2007 Issued
Array ( [id] => 6582 [patent_doc_number] => 07817461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Data storage device using magnetic domain wall movement and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/752397 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3512 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/817/07817461.pdf [firstpage_image] =>[orig_patent_app_number] => 11752397 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/752397
Data storage device using magnetic domain wall movement and method of operating the same May 22, 2007 Issued
Array ( [id] => 5257915 [patent_doc_number] => 20070211547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/797984 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13753 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20070211547.pdf [firstpage_image] =>[orig_patent_app_number] => 11797984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797984
Semiconductor device May 8, 2007 Issued
Array ( [id] => 300861 [patent_doc_number] => 07539068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Memory and multi-state sense amplifier thereof' [patent_app_type] => utility [patent_app_number] => 11/797725 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4059 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539068.pdf [firstpage_image] =>[orig_patent_app_number] => 11797725 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797725
Memory and multi-state sense amplifier thereof May 6, 2007 Issued
Array ( [id] => 5084091 [patent_doc_number] => 20070274142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Method and device of generating test circuit for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/797545 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11084 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20070274142.pdf [firstpage_image] =>[orig_patent_app_number] => 11797545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797545
Method and device of generating test circuit for semiconductor device May 3, 2007 Abandoned
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