
Amanda Lee Bailey
Examiner (ID: 3862)
| Most Active Art Unit | 3673 |
| Art Unit(s) | 3673 |
| Total Applications | 484 |
| Issued Applications | 252 |
| Pending Applications | 47 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 192047
[patent_doc_number] => 07643366
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/797405
[patent_app_country] => US
[patent_app_date] => 2007-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3470
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/643/07643366.pdf
[firstpage_image] =>[orig_patent_app_number] => 11797405
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/797405 | Semiconductor integrated circuit | May 2, 2007 | Issued |
Array
(
[id] => 212459
[patent_doc_number] => 07623371
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-24
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/743515
[patent_app_country] => US
[patent_app_date] => 2007-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 58
[patent_no_of_words] => 21274
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 573
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/623/07623371.pdf
[firstpage_image] =>[orig_patent_app_number] => 11743515
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/743515 | Semiconductor device | May 1, 2007 | Issued |
Array
(
[id] => 360734
[patent_doc_number] => 07486567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Method for high speed programming of a charge trapping memory with an enhanced charge trapping site'
[patent_app_type] => utility
[patent_app_number] => 11/741917
[patent_app_country] => US
[patent_app_date] => 2007-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4395
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/486/07486567.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741917
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741917 | Method for high speed programming of a charge trapping memory with an enhanced charge trapping site | Apr 29, 2007 | Issued |
Array
(
[id] => 5223357
[patent_doc_number] => 20070252623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'SRAM LEAKAGE REDUCTION CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/741647
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5230
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20070252623.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741647
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741647 | SRAM leakage reduction circuit | Apr 26, 2007 | Issued |
Array
(
[id] => 804722
[patent_doc_number] => 07423922
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Defective block handling in a flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/789725
[patent_app_country] => US
[patent_app_date] => 2007-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2377
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/423/07423922.pdf
[firstpage_image] =>[orig_patent_app_number] => 11789725
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/789725 | Defective block handling in a flash memory device | Apr 24, 2007 | Issued |
Array
(
[id] => 135472
[patent_doc_number] => 07697363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-13
[patent_title] => 'Memory device having data input and output ports and memory module and memory system including the same'
[patent_app_type] => utility
[patent_app_number] => 11/783509
[patent_app_country] => US
[patent_app_date] => 2007-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5854
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/697/07697363.pdf
[firstpage_image] =>[orig_patent_app_number] => 11783509
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/783509 | Memory device having data input and output ports and memory module and memory system including the same | Apr 9, 2007 | Issued |
Array
(
[id] => 4836492
[patent_doc_number] => 20080133824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'MEMORY CARD SYSTEM INCLUDING NAND FLASH MEMORY AND SRAM/NOR FLASH MEMORY, AND DATA STORAGE METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/696991
[patent_app_country] => US
[patent_app_date] => 2007-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4811
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20080133824.pdf
[firstpage_image] =>[orig_patent_app_number] => 11696991
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/696991 | Memory card system including NAND flash memory and SRAM/NOR flash memory, and data storage method thereof | Apr 4, 2007 | Issued |
Array
(
[id] => 218150
[patent_doc_number] => 07613057
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-03
[patent_title] => 'Circuit and method for a sense amplifier'
[patent_app_type] => utility
[patent_app_number] => 11/732297
[patent_app_country] => US
[patent_app_date] => 2007-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6544
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/613/07613057.pdf
[firstpage_image] =>[orig_patent_app_number] => 11732297
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/732297 | Circuit and method for a sense amplifier | Apr 2, 2007 | Issued |
Array
(
[id] => 24646
[patent_doc_number] => 07800950
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Memory devices and methods using selective self-boost programming operations'
[patent_app_type] => utility
[patent_app_number] => 11/693119
[patent_app_country] => US
[patent_app_date] => 2007-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5894
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/800/07800950.pdf
[firstpage_image] =>[orig_patent_app_number] => 11693119
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693119 | Memory devices and methods using selective self-boost programming operations | Mar 28, 2007 | Issued |
Array
(
[id] => 4717266
[patent_doc_number] => 20080239788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/693391
[patent_app_country] => US
[patent_app_date] => 2007-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6016
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20080239788.pdf
[firstpage_image] =>[orig_patent_app_number] => 11693391
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693391 | Integrated circuit having a resistively switching memory and method | Mar 28, 2007 | Issued |
Array
(
[id] => 5246297
[patent_doc_number] => 20070242531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'WRITE APPARATUS FOR DDR SDRAM SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/687285
[patent_app_country] => US
[patent_app_date] => 2007-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4634
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20070242531.pdf
[firstpage_image] =>[orig_patent_app_number] => 11687285
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687285 | Write apparatus for DDR SDRAM semiconductor memory device | Mar 15, 2007 | Issued |
Array
(
[id] => 4976046
[patent_doc_number] => 20070217277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'APPARATUS AND METHOD FOR REDUCING THE LEAKAGE CURRENT OF MEMORY CELLS IN THE ENERGY-SAVING MODE'
[patent_app_type] => utility
[patent_app_number] => 11/686509
[patent_app_country] => US
[patent_app_date] => 2007-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8543
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0217/20070217277.pdf
[firstpage_image] =>[orig_patent_app_number] => 11686509
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/686509 | Apparatus and method for reducing the leakage current of memory cells in the energy-saving mode | Mar 14, 2007 | Issued |
Array
(
[id] => 257330
[patent_doc_number] => 07577010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays'
[patent_app_type] => utility
[patent_app_number] => 11/686211
[patent_app_country] => US
[patent_app_date] => 2007-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 33
[patent_no_of_words] => 8518
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/577/07577010.pdf
[firstpage_image] =>[orig_patent_app_number] => 11686211
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/686211 | Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays | Mar 13, 2007 | Issued |
Array
(
[id] => 5246301
[patent_doc_number] => 20070242535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'Semiconductor memory device and defect remedying method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/714867
[patent_app_country] => US
[patent_app_date] => 2007-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 118
[patent_figures_cnt] => 118
[patent_no_of_words] => 51607
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20070242535.pdf
[firstpage_image] =>[orig_patent_app_number] => 11714867
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/714867 | Semiconductor memory device and defect remedying method thereof | Mar 6, 2007 | Issued |
Array
(
[id] => 4725571
[patent_doc_number] => 20080205112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'Apparatus for Hardening a Static Random Access Memory Cell from Single Event Upsets'
[patent_app_type] => utility
[patent_app_number] => 11/678097
[patent_app_country] => US
[patent_app_date] => 2007-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2723
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20080205112.pdf
[firstpage_image] =>[orig_patent_app_number] => 11678097
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/678097 | Apparatus for hardening a static random access memory cell from single event upsets | Feb 22, 2007 | Issued |
Array
(
[id] => 4847596
[patent_doc_number] => 20080184004
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY'
[patent_app_type] => utility
[patent_app_number] => 11/669919
[patent_app_country] => US
[patent_app_date] => 2007-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4591
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20080184004.pdf
[firstpage_image] =>[orig_patent_app_number] => 11669919
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/669919 | Methods and apparatus for using a configuration array similar to an associated data array | Jan 30, 2007 | Issued |
Array
(
[id] => 4844572
[patent_doc_number] => 20080180980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Memory device with an asymmetric layout structure'
[patent_app_type] => utility
[patent_app_number] => 11/699089
[patent_app_country] => US
[patent_app_date] => 2007-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2349
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20080180980.pdf
[firstpage_image] =>[orig_patent_app_number] => 11699089
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/699089 | Memory device with an asymmetric layout structure | Jan 28, 2007 | Issued |
Array
(
[id] => 6366810
[patent_doc_number] => 20100074753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-25
[patent_title] => 'Drive Train between a Rotor and Gear Unit of a Wind Power Plant'
[patent_app_type] => utility
[patent_app_number] => 12/160333
[patent_app_country] => US
[patent_app_date] => 2007-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2501
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20100074753.pdf
[firstpage_image] =>[orig_patent_app_number] => 12160333
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/160333 | Drive train between a rotor and gear unit of a wind power plant | Jan 25, 2007 | Issued |
Array
(
[id] => 589065
[patent_doc_number] => 07453726
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-11-18
[patent_title] => 'Non-volatile memory cell with improved programming technique and density'
[patent_app_type] => utility
[patent_app_number] => 11/656609
[patent_app_country] => US
[patent_app_date] => 2007-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4106
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/453/07453726.pdf
[firstpage_image] =>[orig_patent_app_number] => 11656609
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/656609 | Non-volatile memory cell with improved programming technique and density | Jan 22, 2007 | Issued |
Array
(
[id] => 5246316
[patent_doc_number] => 20070242550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'Device and method of controlling operation of a flash memory'
[patent_app_type] => utility
[patent_app_number] => 11/655865
[patent_app_country] => US
[patent_app_date] => 2007-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1834
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20070242550.pdf
[firstpage_image] =>[orig_patent_app_number] => 11655865
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/655865 | Device and method of controlling operation of a flash memory | Jan 21, 2007 | Abandoned |