Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 441350 [patent_doc_number] => 07260010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Refresh control circuit and method for multi-bank structure DRAM' [patent_app_type] => utility [patent_app_number] => 11/604947 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4611 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/260/07260010.pdf [firstpage_image] =>[orig_patent_app_number] => 11604947 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/604947
Refresh control circuit and method for multi-bank structure DRAM Nov 26, 2006 Issued
Array ( [id] => 5538541 [patent_doc_number] => 20090220346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'Radial Compressor Rotor' [patent_app_type] => utility [patent_app_number] => 12/084920 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3515 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20090220346.pdf [firstpage_image] =>[orig_patent_app_number] => 12084920 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/084920
Radial compressor rotor Oct 29, 2006 Issued
Array ( [id] => 581634 [patent_doc_number] => 07463524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Reading and writing method for non-volatile memory with multiple data states' [patent_app_type] => utility [patent_app_number] => 11/588249 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2288 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463524.pdf [firstpage_image] =>[orig_patent_app_number] => 11588249 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588249
Reading and writing method for non-volatile memory with multiple data states Oct 26, 2006 Issued
Array ( [id] => 4492469 [patent_doc_number] => 07885133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Memory control device' [patent_app_type] => utility [patent_app_number] => 12/090397 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/885/07885133.pdf [firstpage_image] =>[orig_patent_app_number] => 12090397 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/090397
Memory control device Oct 18, 2006 Issued
Array ( [id] => 5153124 [patent_doc_number] => 20070036006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'System and method for mode register control of data bus operating mode and impedance' [patent_app_type] => utility [patent_app_number] => 11/542702 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7449 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20070036006.pdf [firstpage_image] =>[orig_patent_app_number] => 11542702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542702
System and method for mode register control of data bus operating mode and impedance Oct 2, 2006 Issued
Array ( [id] => 5170367 [patent_doc_number] => 20070070798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Internal address generator for use in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/529285 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3519 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070798.pdf [firstpage_image] =>[orig_patent_app_number] => 11529285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/529285
Internal address generator for use in semiconductor memory device Sep 28, 2006 Issued
Array ( [id] => 4942922 [patent_doc_number] => 20080080247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Low voltage low capacitance flash memory array' [patent_app_type] => utility [patent_app_number] => 11/540319 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4267 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080247.pdf [firstpage_image] =>[orig_patent_app_number] => 11540319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540319
Low voltage low capacitance flash memory array Sep 27, 2006 Issued
Array ( [id] => 7596640 [patent_doc_number] => 07619942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Multi-port memory device having self-refresh mode' [patent_app_type] => utility [patent_app_number] => 11/540381 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619942.pdf [firstpage_image] =>[orig_patent_app_number] => 11540381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540381
Multi-port memory device having self-refresh mode Sep 27, 2006 Issued
Array ( [id] => 4590565 [patent_doc_number] => 07852705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Method of and circuit for configuring a plurality of memory elements' [patent_app_type] => utility [patent_app_number] => 11/527887 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/852/07852705.pdf [firstpage_image] =>[orig_patent_app_number] => 11527887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527887
Method of and circuit for configuring a plurality of memory elements Sep 26, 2006 Issued
Array ( [id] => 879232 [patent_doc_number] => 07359251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Non-volatile semiconductor memory device, erase method for same, and test method for same' [patent_app_type] => utility [patent_app_number] => 11/518207 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5602 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359251.pdf [firstpage_image] =>[orig_patent_app_number] => 11518207 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518207
Non-volatile semiconductor memory device, erase method for same, and test method for same Sep 10, 2006 Issued
Array ( [id] => 585713 [patent_doc_number] => 07460396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/470651 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 23471 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/460/07460396.pdf [firstpage_image] =>[orig_patent_app_number] => 11470651 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470651
Semiconductor device Sep 6, 2006 Issued
Array ( [id] => 4703274 [patent_doc_number] => 20080062797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'REFRESH SEQUENCE CONTROL FOR MULTIPLE MEMORY ELEMENTS' [patent_app_type] => utility [patent_app_number] => 11/470903 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20080062797.pdf [firstpage_image] =>[orig_patent_app_number] => 11470903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470903
Refresh sequence control for multiple memory elements Sep 6, 2006 Issued
Array ( [id] => 5170351 [patent_doc_number] => 20070070782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Memory device input buffer, related memory device, controller and system' [patent_app_type] => utility [patent_app_number] => 11/515799 [patent_app_country] => US [patent_app_date] => 2006-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4030 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070782.pdf [firstpage_image] =>[orig_patent_app_number] => 11515799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515799
Memory device input buffer, related memory device, controller and system Sep 5, 2006 Issued
Array ( [id] => 4668448 [patent_doc_number] => 20080043508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Method for Programming one-time Programmable Memory of Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/465589 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2672 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20080043508.pdf [firstpage_image] =>[orig_patent_app_number] => 11465589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465589
Method for programming one-time programmable memory of integrated circuit Aug 17, 2006 Issued
Array ( [id] => 909959 [patent_doc_number] => 07333358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Memory element' [patent_app_type] => utility [patent_app_number] => 11/465209 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4632 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/333/07333358.pdf [firstpage_image] =>[orig_patent_app_number] => 11465209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465209
Memory element Aug 16, 2006 Issued
Array ( [id] => 5094118 [patent_doc_number] => 20070115727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'FLASH MEMORY DEVICE HAVING PUMP WITH MULTIPLE OUTPUT VOLTAGES' [patent_app_type] => utility [patent_app_number] => 11/465323 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4152 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20070115727.pdf [firstpage_image] =>[orig_patent_app_number] => 11465323 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465323
Flash memory device having pump with multiple output voltages Aug 16, 2006 Issued
Array ( [id] => 5074178 [patent_doc_number] => 20070014153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Pipelined Programming of Non-Volatile Memories Using Early Data' [patent_app_type] => utility [patent_app_number] => 11/462946 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13138 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20070014153.pdf [firstpage_image] =>[orig_patent_app_number] => 11462946 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462946
Pipelined programming of non-volatile memories using early data Aug 6, 2006 Issued
Array ( [id] => 4445153 [patent_doc_number] => 07929342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Magnetic memory cell, magnetic random access memory, and data read/write method for magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 11/996711 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 42 [patent_no_of_words] => 18695 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/929/07929342.pdf [firstpage_image] =>[orig_patent_app_number] => 11996711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/996711
Magnetic memory cell, magnetic random access memory, and data read/write method for magnetic random access memory Aug 3, 2006 Issued
Array ( [id] => 572680 [patent_doc_number] => 07471582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Memory circuit using a reference for sensing' [patent_app_type] => utility [patent_app_number] => 11/460745 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2897 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/471/07471582.pdf [firstpage_image] =>[orig_patent_app_number] => 11460745 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460745
Memory circuit using a reference for sensing Jul 27, 2006 Issued
Array ( [id] => 808454 [patent_doc_number] => 07420854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'SRAM device and operating method' [patent_app_type] => utility [patent_app_number] => 11/493345 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3117 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420854.pdf [firstpage_image] =>[orig_patent_app_number] => 11493345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493345
SRAM device and operating method Jul 25, 2006 Issued
Menu