Amanda Lee Bailey

Array ( [id] => 402830 [patent_doc_number] => 07292474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/443119 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 7428 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/292/07292474.pdf [firstpage_image] =>[orig_patent_app_number] => 11443119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 346135 [patent_doc_number] => 07499327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'NAND flash memory device having page buffer adapted to discharge bit line voltage during erase operation' [patent_app_type] => utility [patent_app_number] => 11/443205 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2201 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499327.pdf [firstpage_image] =>[orig_patent_app_number] => 11443205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 815026 [patent_doc_number] => 07414889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Structure and method of sub-gate and architectures employing bandgap engineered SONOS devices' [patent_app_type] => utility [patent_app_number] => 11/419977 [patent_app_country] => US [patent_app_date] => 2006-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7009 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414889.pdf [firstpage_image] =>[orig_patent_app_number] => 11419977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 338996 [patent_doc_number] => 07505341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Low voltage sense amplifier and sensing method' [patent_app_type] => utility [patent_app_number] => 11/436863 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5133 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/505/07505341.pdf [firstpage_image] =>[orig_patent_app_number] => 11436863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 891389 [patent_doc_number] => 07349262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices' [patent_app_type] => utility [patent_app_number] => 11/432375 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4145 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/349/07349262.pdf [firstpage_image] =>[orig_patent_app_number] => 11432375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5044766 [patent_doc_number] => 20070263438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method for reading NAND memory device and memory cell array thereof' [patent_app_type] => utility [patent_app_number] => 11/432501 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6108 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263438.pdf [firstpage_image] =>[orig_patent_app_number] => 11432501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 85827 [patent_doc_number] => 07742357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Securing an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/381824 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4863 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/742/07742357.pdf [firstpage_image] =>[orig_patent_app_number] => 11381824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5015101 [patent_doc_number] => 20070258309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'SECURING AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/381837 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5464 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20070258309.pdf [firstpage_image] =>[orig_patent_app_number] => 11381837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5209376 [patent_doc_number] => 20070247960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'System and method to synchronize signals in individual integrated circuit components' [patent_app_type] => utility [patent_app_number] => 11/408647 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4028 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247960.pdf [firstpage_image] =>[orig_patent_app_number] => 11408647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5833402 [patent_doc_number] => 20060245232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Semiconductor integrated circuit with fuse data read circuit' [patent_app_type] => utility [patent_app_number] => 11/409389 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245232.pdf [firstpage_image] =>[orig_patent_app_number] => 11409389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5203679 [patent_doc_number] => 20070025158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Semiconductor memory device and related programming method' [patent_app_type] => utility [patent_app_number] => 11/407969 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4526 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20070025158.pdf [firstpage_image] =>[orig_patent_app_number] => 11407969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5246315 [patent_doc_number] => 20070242549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'System and method for controlling constant power dissipation' [patent_app_type] => utility [patent_app_number] => 11/406073 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3101 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242549.pdf [firstpage_image] =>[orig_patent_app_number] => 11406073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 387525 [patent_doc_number] => 07304896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Method and circuit for simultaneously programming memory cells' [patent_app_type] => utility [patent_app_number] => 11/279663 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2560 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304896.pdf [firstpage_image] =>[orig_patent_app_number] => 11279663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 924020 [patent_doc_number] => 07319624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof' [patent_app_type] => utility [patent_app_number] => 11/403345 [patent_app_country] => US [patent_app_date] => 2006-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3777 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/319/07319624.pdf [firstpage_image] =>[orig_patent_app_number] => 11403345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 422680 [patent_doc_number] => 07274615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Semiconductor memory device and semiconductor memory device test method' [patent_app_type] => utility [patent_app_number] => 11/376297 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6084 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274615.pdf [firstpage_image] =>[orig_patent_app_number] => 11376297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5235127 [patent_doc_number] => 20070127283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Autonomous antifuse cell' [patent_app_type] => utility [patent_app_number] => 11/375839 [patent_app_country] => US [patent_app_date] => 2006-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6263 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20070127283.pdf [firstpage_image] =>[orig_patent_app_number] => 11375839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5203667 [patent_doc_number] => 20070025146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Sensing circuit for multi-level flash memory' [patent_app_type] => utility [patent_app_number] => 11/362067 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2665 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20070025146.pdf [firstpage_image] =>[orig_patent_app_number] => 11362067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5003706 [patent_doc_number] => 20070201273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Back-gate controlled asymmetrical memory cell and memory using the cell' [patent_app_type] => utility [patent_app_number] => 11/362613 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201273.pdf [firstpage_image] =>[orig_patent_app_number] => 11362613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5654308 [patent_doc_number] => 20060140043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Flash memory architecture for optimizing performance of memory having multi-level memory cells' [patent_app_type] => utility [patent_app_number] => 11/358354 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20060140043.pdf [firstpage_image] =>[orig_patent_app_number] => 11358354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5176383 [patent_doc_number] => 20070177442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Low voltage data path and current sense amplifier' [patent_app_type] => utility [patent_app_number] => 11/358089 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8466 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20070177442.pdf [firstpage_image] =>[orig_patent_app_number] => 11358089 [rel_patent_id] =>[rel_patent_doc_number] =>)