
Amanda Lee Bailey
Examiner (ID: 3862)
| Most Active Art Unit | 3673 |
| Art Unit(s) | 3673 |
| Total Applications | 484 |
| Issued Applications | 252 |
| Pending Applications | 47 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4993421
[patent_doc_number] => 20070008766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-11
[patent_title] => 'Ferroelectric storage device'
[patent_app_type] => utility
[patent_app_number] => 11/258227
[patent_app_country] => US
[patent_app_date] => 2005-10-26
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[pdf_file] => publications/A1/0008/20070008766.pdf
[firstpage_image] =>[orig_patent_app_number] => 11258227
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/258227 | Ferroelectric storage device | Oct 25, 2005 | Issued |
Array
(
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[patent_doc_number] => 07301836
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[patent_issue_date] => 2007-11-27
[patent_title] => 'Feature control circuitry for testing integrated circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/257861 | Feature control circuitry for testing integrated circuits | Oct 24, 2005 | Issued |
Array
(
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[patent_doc_number] => 20080062769
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[patent_title] => 'Memory Device and Method Providing an Average Threshold Based Refresh'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/577711 | Memory device and method providing an average threshold based refresh mechanism | Oct 16, 2005 | Issued |
Array
(
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[patent_title] => 'Non-volatile memory and method with bit line compensation dependent on neighboring operating modes'
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Array
(
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[patent_doc_number] => 20060083077
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[patent_issue_date] => 2006-04-20
[patent_title] => 'Memory device'
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Array
(
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[patent_title] => 'Memory device with a plurality of reference cells on a bit line'
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Array
(
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[patent_title] => 'Nonvolatile semiconductor memory device and write/verify method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/242897 | Nonvolatile semiconductor memory device and write/verify method thereof | Oct 4, 2005 | Issued |
Array
(
[id] => 796221
[patent_doc_number] => 07430140
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[patent_issue_date] => 2008-09-30
[patent_title] => 'Method and device for improved data valid window in response to temperature variation'
[patent_app_type] => utility
[patent_app_number] => 11/234647
[patent_app_country] => US
[patent_app_date] => 2005-09-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/234647 | Method and device for improved data valid window in response to temperature variation | Sep 22, 2005 | Issued |
Array
(
[id] => 5636128
[patent_doc_number] => 20060067101
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[patent_title] => 'Memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229763 | Memory | Sep 19, 2005 | Issued |
Array
(
[id] => 585595
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[patent_issue_date] => 2008-12-02
[patent_title] => 'Low cost high density rectifier matrix memory'
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[patent_app_number] => 11/229941
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[pdf_file] => patents/07/460/07460384.pdf
[firstpage_image] =>[orig_patent_app_number] => 11229941
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229941 | Low cost high density rectifier matrix memory | Sep 18, 2005 | Issued |
Array
(
[id] => 15756
[patent_doc_number] => 07804732
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[patent_issue_date] => 2010-09-28
[patent_title] => 'Memory control with selective retention'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/575865 | Memory control with selective retention | Sep 18, 2005 | Issued |
Array
(
[id] => 883084
[patent_doc_number] => 07355898
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[patent_title] => 'Integrated circuit and method for reading from resistance memory cells'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/227429 | Integrated circuit and method for reading from resistance memory cells | Sep 15, 2005 | Issued |
Array
(
[id] => 815038
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[patent_title] => 'Technique to suppress bitline leakage current'
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Array
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Array
(
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Array
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Array
(
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Array
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Array
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