Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4993421 [patent_doc_number] => 20070008766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Ferroelectric storage device' [patent_app_type] => utility [patent_app_number] => 11/258227 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11482 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20070008766.pdf [firstpage_image] =>[orig_patent_app_number] => 11258227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258227
Ferroelectric storage device Oct 25, 2005 Issued
Array ( [id] => 391238 [patent_doc_number] => 07301836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-27 [patent_title] => 'Feature control circuitry for testing integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/257861 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301836.pdf [firstpage_image] =>[orig_patent_app_number] => 11257861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257861
Feature control circuitry for testing integrated circuits Oct 24, 2005 Issued
Array ( [id] => 4703246 [patent_doc_number] => 20080062769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Memory Device and Method Providing an Average Threshold Based Refresh' [patent_app_type] => utility [patent_app_number] => 11/577711 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6511 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20080062769.pdf [firstpage_image] =>[orig_patent_app_number] => 11577711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/577711
Memory device and method providing an average threshold based refresh mechanism Oct 16, 2005 Issued
Array ( [id] => 5797842 [patent_doc_number] => 20060034121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Non-volatile memory and method with bit line compensation dependent on neighboring operating modes' [patent_app_type] => utility [patent_app_number] => 11/250357 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9721 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20060034121.pdf [firstpage_image] =>[orig_patent_app_number] => 11250357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250357
Non-volatile memory and method with bit line compensation dependent on neighboring operating modes Oct 12, 2005 Issued
Array ( [id] => 5812204 [patent_doc_number] => 20060083077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 11/249763 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4637 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083077.pdf [firstpage_image] =>[orig_patent_app_number] => 11249763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/249763
Memory device Oct 12, 2005 Issued
Array ( [id] => 4981697 [patent_doc_number] => 20070086255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Memory device with a plurality of reference cells on a bit line' [patent_app_type] => utility [patent_app_number] => 11/250005 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20070086255.pdf [firstpage_image] =>[orig_patent_app_number] => 11250005 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250005
Memory device with a plurality of reference cells on a bit line Oct 12, 2005 Issued
Array ( [id] => 7602635 [patent_doc_number] => 07236401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Nonvolatile semiconductor memory device and write/verify method thereof' [patent_app_type] => utility [patent_app_number] => 11/242897 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236401.pdf [firstpage_image] =>[orig_patent_app_number] => 11242897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242897
Nonvolatile semiconductor memory device and write/verify method thereof Oct 4, 2005 Issued
Array ( [id] => 796221 [patent_doc_number] => 07430140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-30 [patent_title] => 'Method and device for improved data valid window in response to temperature variation' [patent_app_type] => utility [patent_app_number] => 11/234647 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/430/07430140.pdf [firstpage_image] =>[orig_patent_app_number] => 11234647 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/234647
Method and device for improved data valid window in response to temperature variation Sep 22, 2005 Issued
Array ( [id] => 5636128 [patent_doc_number] => 20060067101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Memory' [patent_app_type] => utility [patent_app_number] => 11/229763 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067101.pdf [firstpage_image] =>[orig_patent_app_number] => 11229763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229763
Memory Sep 19, 2005 Issued
Array ( [id] => 585595 [patent_doc_number] => 07460384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Low cost high density rectifier matrix memory' [patent_app_type] => utility [patent_app_number] => 11/229941 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2928 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/460/07460384.pdf [firstpage_image] =>[orig_patent_app_number] => 11229941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229941
Low cost high density rectifier matrix memory Sep 18, 2005 Issued
Array ( [id] => 15756 [patent_doc_number] => 07804732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Memory control with selective retention' [patent_app_type] => utility [patent_app_number] => 11/575865 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/804/07804732.pdf [firstpage_image] =>[orig_patent_app_number] => 11575865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/575865
Memory control with selective retention Sep 18, 2005 Issued
Array ( [id] => 883084 [patent_doc_number] => 07355898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Integrated circuit and method for reading from resistance memory cells' [patent_app_type] => utility [patent_app_number] => 11/227429 [patent_app_country] => US [patent_app_date] => 2005-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5981 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355898.pdf [firstpage_image] =>[orig_patent_app_number] => 11227429 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227429
Integrated circuit and method for reading from resistance memory cells Sep 15, 2005 Issued
Array ( [id] => 815038 [patent_doc_number] => 07414896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Technique to suppress bitline leakage current' [patent_app_type] => utility [patent_app_number] => 11/225465 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 4012 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414896.pdf [firstpage_image] =>[orig_patent_app_number] => 11225465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225465
Technique to suppress bitline leakage current Sep 12, 2005 Issued
Array ( [id] => 4662293 [patent_doc_number] => 20080253200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Reading of the State of a Non-Volatile Storage Element' [patent_app_type] => utility [patent_app_number] => 11/662995 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3795 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20080253200.pdf [firstpage_image] =>[orig_patent_app_number] => 11662995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/662995
Reading of the state of a non-volatile storage element Sep 12, 2005 Issued
Array ( [id] => 490086 [patent_doc_number] => 07218552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-15 [patent_title] => 'Last-first mode and method for programming of non-volatile memory with reduced program disturb' [patent_app_type] => utility [patent_app_number] => 11/223623 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 12727 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218552.pdf [firstpage_image] =>[orig_patent_app_number] => 11223623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223623
Last-first mode and method for programming of non-volatile memory with reduced program disturb Sep 8, 2005 Issued
Array ( [id] => 557014 [patent_doc_number] => 07170788 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-30 [patent_title] => 'Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb' [patent_app_type] => utility [patent_app_number] => 11/223273 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 12805 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170788.pdf [firstpage_image] =>[orig_patent_app_number] => 11223273 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223273
Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb Sep 8, 2005 Issued
Array ( [id] => 5147252 [patent_doc_number] => 20070047306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Non-volatile memory copy back' [patent_app_type] => utility [patent_app_number] => 11/215993 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1723 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047306.pdf [firstpage_image] =>[orig_patent_app_number] => 11215993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215993
Non-volatile memory copy back Aug 29, 2005 Issued
Array ( [id] => 5150628 [patent_doc_number] => 20070050688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Memory correction system and method' [patent_app_type] => utility [patent_app_number] => 11/214697 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4388 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20070050688.pdf [firstpage_image] =>[orig_patent_app_number] => 11214697 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214697
Memory correction system and method Aug 29, 2005 Issued
Array ( [id] => 4914280 [patent_doc_number] => 20080094880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Magneto-Resistance Element And Magnetic Random Access Memory' [patent_app_type] => utility [patent_app_number] => 11/661205 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094880.pdf [firstpage_image] =>[orig_patent_app_number] => 11661205 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/661205
Magneto resistance element and magnetic random access memory Aug 25, 2005 Issued
Array ( [id] => 7054932 [patent_doc_number] => 20050276104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Reduced data line pre-fetch scheme' [patent_app_type] => utility [patent_app_number] => 11/207919 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4659 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20050276104.pdf [firstpage_image] =>[orig_patent_app_number] => 11207919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207919
Reduced data line pre-fetch scheme Aug 18, 2005 Issued
Menu