Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5589767 [patent_doc_number] => 20060039218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/206016 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13699 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20060039218.pdf [firstpage_image] =>[orig_patent_app_number] => 11206016 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/206016
Semiconductor device Aug 17, 2005 Issued
Array ( [id] => 5592261 [patent_doc_number] => 20060041714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Method for controlling memories of a plurality of kinds and circuit for controlling memories of a plurality of kinds' [patent_app_type] => utility [patent_app_number] => 11/205221 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4742 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20060041714.pdf [firstpage_image] =>[orig_patent_app_number] => 11205221 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205221
Method for controlling memories of a plurality of kinds and circuit for controlling memories of a plurality of kinds Aug 16, 2005 Issued
Array ( [id] => 5147242 [patent_doc_number] => 20070047296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Memory device that programs more than two states into memory cell' [patent_app_type] => utility [patent_app_number] => 11/204201 [patent_app_country] => US [patent_app_date] => 2005-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7307 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047296.pdf [firstpage_image] =>[orig_patent_app_number] => 11204201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204201
Integrated circuit having resistive memory Aug 14, 2005 Issued
Array ( [id] => 5153122 [patent_doc_number] => 20070036004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Hybrid non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/201247 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20070036004.pdf [firstpage_image] =>[orig_patent_app_number] => 11201247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201247
Hybrid non-volatile memory device Aug 9, 2005 Issued
Array ( [id] => 475496 [patent_doc_number] => 07230845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Magnetic devices having a hard bias field and magnetic memory devices using the magnetic devices' [patent_app_type] => utility [patent_app_number] => 11/192811 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6383 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230845.pdf [firstpage_image] =>[orig_patent_app_number] => 11192811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/192811
Magnetic devices having a hard bias field and magnetic memory devices using the magnetic devices Jul 28, 2005 Issued
Array ( [id] => 478603 [patent_doc_number] => 07227778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Semiconductor device and writing method' [patent_app_type] => utility [patent_app_number] => 11/194023 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7365 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227778.pdf [firstpage_image] =>[orig_patent_app_number] => 11194023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194023
Semiconductor device and writing method Jul 28, 2005 Issued
Array ( [id] => 919747 [patent_doc_number] => 07324388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/189977 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 65 [patent_no_of_words] => 15093 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/324/07324388.pdf [firstpage_image] =>[orig_patent_app_number] => 11189977 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/189977
Nonvolatile memory Jul 26, 2005 Issued
Array ( [id] => 433627 [patent_doc_number] => 07266020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-04 [patent_title] => 'Method and apparatus for address and data line usage in a multiple context programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/184375 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266020.pdf [firstpage_image] =>[orig_patent_app_number] => 11184375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/184375
Method and apparatus for address and data line usage in a multiple context programmable logic device Jul 18, 2005 Issued
Array ( [id] => 5825390 [patent_doc_number] => 20060062065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Sense amplifier circuit' [patent_app_type] => utility [patent_app_number] => 11/178301 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1423 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20060062065.pdf [firstpage_image] =>[orig_patent_app_number] => 11178301 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/178301
Sense amplifier circuit Jul 11, 2005 Issued
Array ( [id] => 870838 [patent_doc_number] => 07366050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Apparatus and method for data outputting' [patent_app_type] => utility [patent_app_number] => 11/178561 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3608 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366050.pdf [firstpage_image] =>[orig_patent_app_number] => 11178561 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/178561
Apparatus and method for data outputting Jul 11, 2005 Issued
Array ( [id] => 874791 [patent_doc_number] => 07362604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements' [patent_app_type] => utility [patent_app_number] => 11/179077 [patent_app_country] => US [patent_app_date] => 2005-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14008 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362604.pdf [firstpage_image] =>[orig_patent_app_number] => 11179077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/179077
Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements Jul 10, 2005 Issued
Array ( [id] => 5900592 [patent_doc_number] => 20060044904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Bit line sense amplifier control circuit' [patent_app_type] => utility [patent_app_number] => 11/152111 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2070 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044904.pdf [firstpage_image] =>[orig_patent_app_number] => 11152111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152111
Bit line sense amplifier control circuit Jun 14, 2005 Issued
Array ( [id] => 624909 [patent_doc_number] => 07139190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-21 [patent_title] => 'Single event upset tolerant memory cell layout' [patent_app_type] => utility [patent_app_number] => 11/152503 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139190.pdf [firstpage_image] =>[orig_patent_app_number] => 11152503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152503
Single event upset tolerant memory cell layout Jun 13, 2005 Issued
Array ( [id] => 5893683 [patent_doc_number] => 20060002221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Refresh counter circuit and control method for refresh operation' [patent_app_type] => utility [patent_app_number] => 11/151553 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8388 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20060002221.pdf [firstpage_image] =>[orig_patent_app_number] => 11151553 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151553
Refresh counter circuit and control method for refresh operation Jun 13, 2005 Issued
Array ( [id] => 503172 [patent_doc_number] => 07209376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Stacked semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/151213 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4515 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/209/07209376.pdf [firstpage_image] =>[orig_patent_app_number] => 11151213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151213
Stacked semiconductor memory device Jun 13, 2005 Issued
Array ( [id] => 543212 [patent_doc_number] => 07180816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Address coding method and address decoder for reducing sensing noise during refresh operation of memory device' [patent_app_type] => utility [patent_app_number] => 11/152449 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2728 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180816.pdf [firstpage_image] =>[orig_patent_app_number] => 11152449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152449
Address coding method and address decoder for reducing sensing noise during refresh operation of memory device Jun 13, 2005 Issued
Array ( [id] => 568750 [patent_doc_number] => 07161831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Leaf plot analysis technique for multiple-side operated devices' [patent_app_type] => utility [patent_app_number] => 11/150799 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1915 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161831.pdf [firstpage_image] =>[orig_patent_app_number] => 11150799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/150799
Leaf plot analysis technique for multiple-side operated devices Jun 9, 2005 Issued
Array ( [id] => 413280 [patent_doc_number] => 07283380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-16 [patent_title] => 'Content addressable memory with selective error logging' [patent_app_type] => utility [patent_app_number] => 11/138512 [patent_app_country] => US [patent_app_date] => 2005-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 40 [patent_no_of_words] => 25642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/283/07283380.pdf [firstpage_image] =>[orig_patent_app_number] => 11138512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/138512
Content addressable memory with selective error logging May 24, 2005 Issued
Array ( [id] => 6962382 [patent_doc_number] => 20050216723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/133790 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216723.pdf [firstpage_image] =>[orig_patent_app_number] => 11133790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/133790
Non-volatile semiconductor memory device May 18, 2005 Issued
Array ( [id] => 617840 [patent_doc_number] => 07145798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Methods for fabricating a magnetic keeper for a memory device' [patent_app_type] => utility [patent_app_number] => 11/132798 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5946 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/145/07145798.pdf [firstpage_image] =>[orig_patent_app_number] => 11132798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/132798
Methods for fabricating a magnetic keeper for a memory device May 18, 2005 Issued
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