Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7211483 [patent_doc_number] => 20050259486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Repair of memory cells' [patent_app_type] => utility [patent_app_number] => 11/128697 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2821 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20050259486.pdf [firstpage_image] =>[orig_patent_app_number] => 11128697 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128697
Repair of memory cells May 11, 2005 Issued
Array ( [id] => 486971 [patent_doc_number] => 07221603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Defective block handling in a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/127465 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2581 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221603.pdf [firstpage_image] =>[orig_patent_app_number] => 11127465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127465
Defective block handling in a flash memory device May 11, 2005 Issued
Array ( [id] => 5775506 [patent_doc_number] => 20060104146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Word line driving circuit of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/126677 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2355 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20060104146.pdf [firstpage_image] =>[orig_patent_app_number] => 11126677 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126677
Word line driving circuit of semiconductor memory device May 10, 2005 Issued
Array ( [id] => 6943615 [patent_doc_number] => 20050195664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Semiconductor device saving data in non-volatile manner during standby' [patent_app_type] => utility [patent_app_number] => 11/119937 [patent_app_country] => US [patent_app_date] => 2005-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10614 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195664.pdf [firstpage_image] =>[orig_patent_app_number] => 11119937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/119937
Semiconductor device saving data in non-volatile manner during standby May 2, 2005 Issued
Array ( [id] => 7068254 [patent_doc_number] => 20050243637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Method for programming a memory arrangement and programmed memory arrangement' [patent_app_type] => utility [patent_app_number] => 11/115031 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3528 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20050243637.pdf [firstpage_image] =>[orig_patent_app_number] => 11115031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/115031
Method for programming a memory arrangement and programmed memory arrangement Apr 25, 2005 Issued
Array ( [id] => 5767971 [patent_doc_number] => 20050265095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/114165 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20050265095.pdf [firstpage_image] =>[orig_patent_app_number] => 11114165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/114165
Semiconductor integrated circuit Apr 25, 2005 Issued
Array ( [id] => 6924541 [patent_doc_number] => 20050237796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'MRAM element' [patent_app_type] => utility [patent_app_number] => 11/114305 [patent_app_country] => US [patent_app_date] => 2005-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10046 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20050237796.pdf [firstpage_image] =>[orig_patent_app_number] => 11114305 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/114305
MRAM element Apr 24, 2005 Issued
Array ( [id] => 7165073 [patent_doc_number] => 20050201138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Nonvolatile feram control device' [patent_app_type] => utility [patent_app_number] => 11/104579 [patent_app_country] => US [patent_app_date] => 2005-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6700 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20050201138.pdf [firstpage_image] =>[orig_patent_app_number] => 11104579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/104579
Nonvolatile FeRam control device Apr 12, 2005 Issued
Array ( [id] => 7132827 [patent_doc_number] => 20050179058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Semiconductor memory device and defect remedying method thereof' [patent_app_type] => utility [patent_app_number] => 11/101504 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 118 [patent_figures_cnt] => 118 [patent_no_of_words] => 51367 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20050179058.pdf [firstpage_image] =>[orig_patent_app_number] => 11101504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/101504
Semiconductor memory device and defect remedying method thereof Apr 7, 2005 Issued
Array ( [id] => 573179 [patent_doc_number] => 07158433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Semiconductor storage device and method of controlling refreshing of semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/097247 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7631 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/158/07158433.pdf [firstpage_image] =>[orig_patent_app_number] => 11097247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097247
Semiconductor storage device and method of controlling refreshing of semiconductor storage device Apr 3, 2005 Issued
Array ( [id] => 531658 [patent_doc_number] => 07187596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Semiconductor system having a source potential supply section' [patent_app_type] => utility [patent_app_number] => 11/097359 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5956 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187596.pdf [firstpage_image] =>[orig_patent_app_number] => 11097359 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097359
Semiconductor system having a source potential supply section Apr 3, 2005 Issued
Array ( [id] => 5752548 [patent_doc_number] => 20060221697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'USE OF DATA LATCHES IN MULTI-PHASE PROGRAMMING OF NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 11/097517 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14321 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20060221697.pdf [firstpage_image] =>[orig_patent_app_number] => 11097517 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097517
Use of data latches in multi-phase programming of non-volatile memories Mar 31, 2005 Issued
Array ( [id] => 7180235 [patent_doc_number] => 20050190631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Method for bus capacitance reduction' [patent_app_type] => utility [patent_app_number] => 11/089521 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4080 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20050190631.pdf [firstpage_image] =>[orig_patent_app_number] => 11089521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089521
Method for bus capacitance reduction Mar 23, 2005 Issued
Array ( [id] => 7038108 [patent_doc_number] => 20050157542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Magnetoresistive element and magnetic memory unit' [patent_app_type] => utility [patent_app_number] => 11/078942 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11062 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20050157542.pdf [firstpage_image] =>[orig_patent_app_number] => 11078942 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078942
Magnetoresistive element and magnetic memory unit Mar 10, 2005 Abandoned
Array ( [id] => 786458 [patent_doc_number] => 06990014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Magnetoresistive element and magnetic memory unit' [patent_app_type] => utility [patent_app_number] => 11/078976 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11067 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990014.pdf [firstpage_image] =>[orig_patent_app_number] => 11078976 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078976
Magnetoresistive element and magnetic memory unit Mar 10, 2005 Issued
Array ( [id] => 7165071 [patent_doc_number] => 20050201137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Ferroelectric memory device and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/076291 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5810 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20050201137.pdf [firstpage_image] =>[orig_patent_app_number] => 11076291 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/076291
Ferroelectric memory device and electronic apparatus Mar 8, 2005 Issued
Array ( [id] => 7017874 [patent_doc_number] => 20050219892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Method of multi-level cell FeRAM' [patent_app_type] => utility [patent_app_number] => 11/064315 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2890 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20050219892.pdf [firstpage_image] =>[orig_patent_app_number] => 11064315 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064315
Method of multi-level cell FeRAM Feb 22, 2005 Issued
Array ( [id] => 554447 [patent_doc_number] => 07167398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-23 [patent_title] => 'System and method for erasing a memory cell' [patent_app_type] => utility [patent_app_number] => 11/062641 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3087 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167398.pdf [firstpage_image] =>[orig_patent_app_number] => 11062641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062641
System and method for erasing a memory cell Feb 22, 2005 Issued
Array ( [id] => 674433 [patent_doc_number] => 07092291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Nonvolatile semiconductor memory device, charge injection method thereof and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/061623 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7312 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/092/07092291.pdf [firstpage_image] =>[orig_patent_app_number] => 11061623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061623
Nonvolatile semiconductor memory device, charge injection method thereof and electronic apparatus Feb 21, 2005 Issued
Array ( [id] => 7003738 [patent_doc_number] => 20050169051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Writable tracking cells' [patent_app_type] => utility [patent_app_number] => 11/064529 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11170 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20050169051.pdf [firstpage_image] =>[orig_patent_app_number] => 11064529 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064529
Writable tracking cells Feb 21, 2005 Issued
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