Amanda Lee Bailey

Array ( [id] => 661126 [patent_doc_number] => 07106628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Semiconductor device having enhanced breakdown voltage' [patent_app_type] => utility [patent_app_number] => 11/061475 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 5225 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106628.pdf [firstpage_image] =>[orig_patent_app_number] => 11061475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6943588 [patent_doc_number] => 20050195637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Biasing structure for accessing semiconductor memory cell storage elements' [patent_app_type] => utility [patent_app_number] => 11/063651 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5142 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195637.pdf [firstpage_image] =>[orig_patent_app_number] => 11063651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 494556 [patent_doc_number] => 07215579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-08 [patent_title] => 'System and method for mode register control of data bus operating mode and impedance' [patent_app_type] => utility [patent_app_number] => 11/061035 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7486 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/215/07215579.pdf [firstpage_image] =>[orig_patent_app_number] => 11061035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5812173 [patent_doc_number] => 20060083047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Nonvolatile memory for logic circuits' [patent_app_type] => utility [patent_app_number] => 11/061951 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9738 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083047.pdf [firstpage_image] =>[orig_patent_app_number] => 11061951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5797859 [patent_doc_number] => 20060034128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Non-volatile memory device and erase method of the same' [patent_app_type] => utility [patent_app_number] => 11/060915 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5279 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20060034128.pdf [firstpage_image] =>[orig_patent_app_number] => 11060915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5009506 [patent_doc_number] => 20070279984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Nonvolatile Semiconductor Storing Device and Block Redundancy Saving Method' [patent_app_type] => utility [patent_app_number] => 10/589101 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7456 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279984.pdf [firstpage_image] =>[orig_patent_app_number] => 10589101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 723456 [patent_doc_number] => 07050347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/038025 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4518 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/050/07050347.pdf [firstpage_image] =>[orig_patent_app_number] => 11038025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6943582 [patent_doc_number] => 20050195631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Method and apparatus for storing and reading information in a ferroelectric material' [patent_app_type] => utility [patent_app_number] => 11/034219 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4388 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195631.pdf [firstpage_image] =>[orig_patent_app_number] => 11034219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7073671 [patent_doc_number] => 20050146938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Transistor with nanocrystalline silicon gate structure' [patent_app_type] => utility [patent_app_number] => 11/028475 [patent_app_country] => US [patent_app_date] => 2005-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3123 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146938.pdf [firstpage_image] =>[orig_patent_app_number] => 11028475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7211518 [patent_doc_number] => 20050259492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Semiconductor memory device and memory system' [patent_app_type] => utility [patent_app_number] => 11/024737 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14738 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20050259492.pdf [firstpage_image] =>[orig_patent_app_number] => 11024737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 921094 [patent_doc_number] => 07321523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'System for monitoring processing device utilization in a computer' [patent_app_type] => utility [patent_app_number] => 10/905363 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321523.pdf [firstpage_image] =>[orig_patent_app_number] => 10905363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5871395 [patent_doc_number] => 20060164902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Pseudo-synchronization of the transportation of data across asynchronous clock domains' [patent_app_type] => utility [patent_app_number] => 11/024351 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2909 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20060164902.pdf [firstpage_image] =>[orig_patent_app_number] => 11024351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5654265 [patent_doc_number] => 20060140000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Operation methods for a non-volatile memory cell in an array' [patent_app_type] => utility [patent_app_number] => 11/020269 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3220 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20060140000.pdf [firstpage_image] =>[orig_patent_app_number] => 11020269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 678453 [patent_doc_number] => 07088631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Semiconductor storage apparatus' [patent_app_type] => utility [patent_app_number] => 11/019271 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 607 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088631.pdf [firstpage_image] =>[orig_patent_app_number] => 11019271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7038098 [patent_doc_number] => 20050157532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Ferroelectric memory device, electronic apparatus and driving method' [patent_app_type] => utility [patent_app_number] => 11/022371 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20050157532.pdf [firstpage_image] =>[orig_patent_app_number] => 11022371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5900652 [patent_doc_number] => 20060044923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Programming circuits and methods for multimode non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 11/020517 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6461 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044923.pdf [firstpage_image] =>[orig_patent_app_number] => 11020517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5647430 [patent_doc_number] => 20060133162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Self-latched control circuit for memory program operation' [patent_app_type] => utility [patent_app_number] => 11/021117 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2580 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133162.pdf [firstpage_image] =>[orig_patent_app_number] => 11021117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 617896 [patent_doc_number] => 07145827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Refresh control circuit and method for multi-bank structure DRAM' [patent_app_type] => utility [patent_app_number] => 11/020803 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4585 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/145/07145827.pdf [firstpage_image] =>[orig_patent_app_number] => 11020803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7245505 [patent_doc_number] => 20050141299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Semiconductor memory device for controlling cell block with state machine' [patent_app_type] => utility [patent_app_number] => 11/015475 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3540 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141299.pdf [firstpage_image] =>[orig_patent_app_number] => 11015475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 939229 [patent_doc_number] => 06972999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/014863 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 43 [patent_no_of_words] => 24610 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972999.pdf [firstpage_image] =>[orig_patent_app_number] => 11014863 [rel_patent_id] =>[rel_patent_doc_number] =>)