Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7059870 [patent_doc_number] => 20050002230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Magnetic memory device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/895841 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002230.pdf [firstpage_image] =>[orig_patent_app_number] => 10895841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895841
Magnetic memory device and manufacturing method thereof Jul 21, 2004 Issued
Array ( [id] => 7619111 [patent_doc_number] => 06944078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/892271 [patent_app_country] => US [patent_app_date] => 2004-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13834 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944078.pdf [firstpage_image] =>[orig_patent_app_number] => 10892271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/892271
Semiconductor device Jul 15, 2004 Issued
Array ( [id] => 592280 [patent_doc_number] => 07450459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Multi-port memory device' [patent_app_type] => utility [patent_app_number] => 10/877837 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5529 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/450/07450459.pdf [firstpage_image] =>[orig_patent_app_number] => 10877837 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877837
Multi-port memory device Jun 24, 2004 Issued
Array ( [id] => 6924546 [patent_doc_number] => 20050237801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Operation scheme with charge balancing for charge trapping non-volatile memory' [patent_app_type] => utility [patent_app_number] => 10/875623 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 17363 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20050237801.pdf [firstpage_image] =>[orig_patent_app_number] => 10875623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875623
Operation scheme with charge balancing for charge trapping non-volatile memory Jun 23, 2004 Issued
Array ( [id] => 6911069 [patent_doc_number] => 20050174827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => '[DEVICE AND METHOD FOR COMPENSATING DEFECT IN SEMICONDUCTOR MEMORY]' [patent_app_type] => utility [patent_app_number] => 10/710123 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5193 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174827.pdf [firstpage_image] =>[orig_patent_app_number] => 10710123 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710123
Device and method for compensating defect in semiconductor memory Jun 20, 2004 Issued
Array ( [id] => 7611873 [patent_doc_number] => 06903966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/863748 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 7726 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903966.pdf [firstpage_image] =>[orig_patent_app_number] => 10863748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863748
Semiconductor device Jun 8, 2004 Issued
Array ( [id] => 7415521 [patent_doc_number] => 20040264261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Controller and method for writing data' [patent_app_type] => new [patent_app_number] => 10/852019 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5533 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20040264261.pdf [firstpage_image] =>[orig_patent_app_number] => 10852019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/852019
Controller and method for writing data May 23, 2004 Issued
Array ( [id] => 7293462 [patent_doc_number] => 20040213036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode' [patent_app_type] => new [patent_app_number] => 10/851879 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4211 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213036.pdf [firstpage_image] =>[orig_patent_app_number] => 10851879 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851879
Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode May 19, 2004 Issued
Array ( [id] => 7274280 [patent_doc_number] => 20040233731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor memory device, driving method thereof, and portable electronic apparatus' [patent_app_type] => new [patent_app_number] => 10/847627 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 20415 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233731.pdf [firstpage_image] =>[orig_patent_app_number] => 10847627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847627
Semiconductor memory device, driving method thereof, and portable electronic apparatus May 17, 2004 Issued
Array ( [id] => 7274268 [patent_doc_number] => 20040233719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor memory device and portable electronic apparatus' [patent_app_type] => new [patent_app_number] => 10/847625 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19995 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233719.pdf [firstpage_image] =>[orig_patent_app_number] => 10847625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847625
Semiconductor memory device and portable electronic apparatus May 17, 2004 Issued
Array ( [id] => 710458 [patent_doc_number] => 07061787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Field ramp down for pinned synthetic antiferromagnet' [patent_app_type] => utility [patent_app_number] => 10/835623 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061787.pdf [firstpage_image] =>[orig_patent_app_number] => 10835623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/835623
Field ramp down for pinned synthetic antiferromagnet Apr 29, 2004 Issued
Array ( [id] => 718911 [patent_doc_number] => 07054203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'High reliability memory element with improved delay time' [patent_app_type] => utility [patent_app_number] => 10/834627 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5103 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/054/07054203.pdf [firstpage_image] =>[orig_patent_app_number] => 10834627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834627
High reliability memory element with improved delay time Apr 27, 2004 Issued
Array ( [id] => 7619127 [patent_doc_number] => 06944062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Transistor and semiconductor memory using the same' [patent_app_type] => utility [patent_app_number] => 10/831333 [patent_app_country] => US [patent_app_date] => 2004-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 60 [patent_no_of_words] => 21586 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944062.pdf [firstpage_image] =>[orig_patent_app_number] => 10831333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831333
Transistor and semiconductor memory using the same Apr 25, 2004 Issued
Array ( [id] => 714004 [patent_doc_number] => 07057948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Semiconductor integrated circuit device having a test function' [patent_app_type] => utility [patent_app_number] => 10/829949 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4210 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057948.pdf [firstpage_image] =>[orig_patent_app_number] => 10829949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/829949
Semiconductor integrated circuit device having a test function Apr 22, 2004 Issued
Array ( [id] => 557088 [patent_doc_number] => 07170793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Programming inhibit for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 10/823421 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 13879 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170793.pdf [firstpage_image] =>[orig_patent_app_number] => 10823421 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/823421
Programming inhibit for non-volatile memory Apr 12, 2004 Issued
Array ( [id] => 7017870 [patent_doc_number] => 20050219888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Multistage parallel-to-serial conversion of read data in memories, with the first serial bit skipping at least one stage' [patent_app_type] => utility [patent_app_number] => 10/816727 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7520 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20050219888.pdf [firstpage_image] =>[orig_patent_app_number] => 10816727 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816727
Multistage parallel-to-serial conversion of read data in memories, with the first serial bit skipping at least one stage Apr 1, 2004 Issued
Array ( [id] => 6916889 [patent_doc_number] => 20050094450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Semiconductor device and testing apparatus for semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/815825 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8827 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20050094450.pdf [firstpage_image] =>[orig_patent_app_number] => 10815825 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815825
Semiconductor device and testing apparatus for semiconductor device Apr 1, 2004 Issued
Array ( [id] => 6943592 [patent_doc_number] => 20050195641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Memory system and associated methodology' [patent_app_type] => utility [patent_app_number] => 10/791131 [patent_app_country] => US [patent_app_date] => 2004-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3886 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195641.pdf [firstpage_image] =>[orig_patent_app_number] => 10791131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/791131
Memory system and associated methodology Mar 1, 2004 Issued
Array ( [id] => 7274271 [patent_doc_number] => 20040233722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Gate voltage regulation system for a non volatile memory cells programming and/or soft programming phase' [patent_app_type] => new [patent_app_number] => 10/788525 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233722.pdf [firstpage_image] =>[orig_patent_app_number] => 10788525 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/788525
Gate voltage regulation system for a non-volatile memory cells programming and/or soft programming phase Feb 25, 2004 Issued
Array ( [id] => 657269 [patent_doc_number] => 07110300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Method of programming a multi-level, electrically programmable non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/782725 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6134 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/110/07110300.pdf [firstpage_image] =>[orig_patent_app_number] => 10782725 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782725
Method of programming a multi-level, electrically programmable non-volatile semiconductor memory Feb 18, 2004 Issued
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