
Amanda Lee Bailey
Examiner (ID: 3862)
| Most Active Art Unit | 3673 |
| Art Unit(s) | 3673 |
| Total Applications | 484 |
| Issued Applications | 252 |
| Pending Applications | 47 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1208599
[patent_doc_number] => 06717835
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-06
[patent_title] => 'Semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/347804
[patent_app_country] => US
[patent_app_date] => 2003-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 13767
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/717/06717835.pdf
[firstpage_image] =>[orig_patent_app_number] => 10347804
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/347804 | Semiconductor device | Jan 21, 2003 | Issued |
Array
(
[id] => 7306339
[patent_doc_number] => 20040141371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'FLOATING GATE ANALOG VOLTAGE FEEDBACK CIRCUIT'
[patent_app_type] => new
[patent_app_number] => 10/348929
[patent_app_country] => US
[patent_app_date] => 2003-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 18141
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20040141371.pdf
[firstpage_image] =>[orig_patent_app_number] => 10348929
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/348929 | Floating gate analog voltage feedback circuit | Jan 20, 2003 | Issued |
Array
(
[id] => 7268790
[patent_doc_number] => 20040057308
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Semiconductor storage device'
[patent_app_type] => new
[patent_app_number] => 10/319591
[patent_app_country] => US
[patent_app_date] => 2002-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6657
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20040057308.pdf
[firstpage_image] =>[orig_patent_app_number] => 10319591
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/319591 | Semiconductor storage device | Dec 15, 2002 | Issued |
Array
(
[id] => 6667672
[patent_doc_number] => 20030112655
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-19
[patent_title] => 'Magnetic memory device and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/316911
[patent_app_country] => US
[patent_app_date] => 2002-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10145
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0112/20030112655.pdf
[firstpage_image] =>[orig_patent_app_number] => 10316911
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/316911 | Magnetic memory device and manufacturing method thereof | Dec 11, 2002 | Issued |
Array
(
[id] => 6667707
[patent_doc_number] => 20030112690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-19
[patent_title] => 'Dynamic semiconductor memory device and method of controlling refresh thereof'
[patent_app_type] => new
[patent_app_number] => 10/317553
[patent_app_country] => US
[patent_app_date] => 2002-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12555
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0112/20030112690.pdf
[firstpage_image] =>[orig_patent_app_number] => 10317553
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/317553 | Dynamic semiconductor memory device and method of controlling refresh thereof | Dec 11, 2002 | Issued |
Array
(
[id] => 7287883
[patent_doc_number] => 20040109358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Refined gate coupled noise compensation for open-drain output from semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/315323
[patent_app_country] => US
[patent_app_date] => 2002-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7666
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20040109358.pdf
[firstpage_image] =>[orig_patent_app_number] => 10315323
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/315323 | Flash memory architecture for optimizing performance of memory having multi-level memory cells | Dec 9, 2002 | Issued |
Array
(
[id] => 7287862
[patent_doc_number] => 20040109345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Chopper sensor for MRAM'
[patent_app_type] => new
[patent_app_number] => 10/314111
[patent_app_country] => US
[patent_app_date] => 2002-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3796
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20040109345.pdf
[firstpage_image] =>[orig_patent_app_number] => 10314111
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/314111 | Chopper sensor for MRAM | Dec 6, 2002 | Issued |
Array
(
[id] => 7331177
[patent_doc_number] => 20040130963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Program counting circuit and program word line voltage generating circuit in flash memory device using the same'
[patent_app_type] => new
[patent_app_number] => 10/310871
[patent_app_country] => US
[patent_app_date] => 2002-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6286
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20040130963.pdf
[firstpage_image] =>[orig_patent_app_number] => 10310871
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/310871 | Program counting circuit and program word line voltage generating circuit in flash memory device using the same | Dec 5, 2002 | Issued |
Array
(
[id] => 1070196
[patent_doc_number] => 06845049
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time'
[patent_app_type] => utility
[patent_app_number] => 10/313817
[patent_app_country] => US
[patent_app_date] => 2002-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3802
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/845/06845049.pdf
[firstpage_image] =>[orig_patent_app_number] => 10313817
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313817 | Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time | Dec 4, 2002 | Issued |
Array
(
[id] => 1070182
[patent_doc_number] => 06845043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'Method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled'
[patent_app_type] => utility
[patent_app_number] => 10/310623
[patent_app_country] => US
[patent_app_date] => 2002-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 29
[patent_no_of_words] => 11609
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/845/06845043.pdf
[firstpage_image] =>[orig_patent_app_number] => 10310623
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/310623 | Method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled | Dec 4, 2002 | Issued |
Array
(
[id] => 6855100
[patent_doc_number] => 20030128601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => 'Folded memory layers'
[patent_app_type] => new
[patent_app_number] => 10/306229
[patent_app_country] => US
[patent_app_date] => 2002-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3286
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20030128601.pdf
[firstpage_image] =>[orig_patent_app_number] => 10306229
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/306229 | Folded memory layers | Nov 28, 2002 | Issued |
Array
(
[id] => 7401613
[patent_doc_number] => 20040105293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-03
[patent_title] => 'Reducing effects of noise coupling in integrated circuits with memory arrays'
[patent_app_type] => new
[patent_app_number] => 10/065921
[patent_app_country] => US
[patent_app_date] => 2002-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2937
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20040105293.pdf
[firstpage_image] =>[orig_patent_app_number] => 10065921
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/065921 | Reducing effects of noise coupling in integrated circuits with memory arrays | Nov 28, 2002 | Issued |
Array
(
[id] => 947192
[patent_doc_number] => 06965527
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-15
[patent_title] => 'Multibank memory on a die'
[patent_app_type] => utility
[patent_app_number] => 10/305715
[patent_app_country] => US
[patent_app_date] => 2002-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6414
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/965/06965527.pdf
[firstpage_image] =>[orig_patent_app_number] => 10305715
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305715 | Multibank memory on a die | Nov 26, 2002 | Issued |
Array
(
[id] => 7195423
[patent_doc_number] => 20040085813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Multiple level RAM device'
[patent_app_type] => new
[patent_app_number] => 10/305051
[patent_app_country] => US
[patent_app_date] => 2002-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3473
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20040085813.pdf
[firstpage_image] =>[orig_patent_app_number] => 10305051
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305051 | Multiple level RAM device | Nov 25, 2002 | Issued |
Array
(
[id] => 7459353
[patent_doc_number] => 20040100815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-27
[patent_title] => 'SRAM bit-line reduction'
[patent_app_type] => new
[patent_app_number] => 10/305753
[patent_app_country] => US
[patent_app_date] => 2002-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1582
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20040100815.pdf
[firstpage_image] =>[orig_patent_app_number] => 10305753
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305753 | SRAM bit-line reduction | Nov 25, 2002 | Issued |
Array
(
[id] => 6800273
[patent_doc_number] => 20030095437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 10/302771
[patent_app_country] => US
[patent_app_date] => 2002-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5430
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20030095437.pdf
[firstpage_image] =>[orig_patent_app_number] => 10302771
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/302771 | Non-volatile semiconductor memory device | Nov 20, 2002 | Issued |
Array
(
[id] => 1095602
[patent_doc_number] => 06826099
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-30
[patent_title] => '2T2C signal margin test mode using a defined charge and discharge of BL and /BL'
[patent_app_type] => B2
[patent_app_number] => 10/301529
[patent_app_country] => US
[patent_app_date] => 2002-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2745
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/826/06826099.pdf
[firstpage_image] =>[orig_patent_app_number] => 10301529
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/301529 | 2T2C signal margin test mode using a defined charge and discharge of BL and /BL | Nov 19, 2002 | Issued |
Array
(
[id] => 6800277
[patent_doc_number] => 20030095441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Semiconductor memory having storage cells storing multiple bits and a method of driving the same'
[patent_app_type] => new
[patent_app_number] => 10/300027
[patent_app_country] => US
[patent_app_date] => 2002-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 14170
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20030095441.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300027
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300027 | Semiconductor memory having storage cells storing multiple bits and a method of driving the same | Nov 19, 2002 | Issued |
Array
(
[id] => 7465292
[patent_doc_number] => 20040095838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-20
[patent_title] => 'Controlling data strobe output'
[patent_app_type] => new
[patent_app_number] => 10/294425
[patent_app_country] => US
[patent_app_date] => 2002-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7416
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20040095838.pdf
[firstpage_image] =>[orig_patent_app_number] => 10294425
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/294425 | Controlling data strobe output | Nov 13, 2002 | Issued |
Array
(
[id] => 931946
[patent_doc_number] => 06980457
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-27
[patent_title] => 'Thyristor-based device having a reduced-resistance contact to a buried emitter region'
[patent_app_type] => utility
[patent_app_number] => 10/288927
[patent_app_country] => US
[patent_app_date] => 2002-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4099
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/980/06980457.pdf
[firstpage_image] =>[orig_patent_app_number] => 10288927
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/288927 | Thyristor-based device having a reduced-resistance contact to a buried emitter region | Nov 5, 2002 | Issued |