Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6728842 [patent_doc_number] => 20030185032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Dual bus memory controller' [patent_app_type] => new [patent_app_number] => 10/108243 [patent_app_country] => US [patent_app_date] => 2002-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4190 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20030185032.pdf [firstpage_image] =>[orig_patent_app_number] => 10108243 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/108243
Dual bus memory controller Mar 25, 2002 Issued
Array ( [id] => 1426225 [patent_doc_number] => 06510090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 10/103721 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4442 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510090.pdf [firstpage_image] =>[orig_patent_app_number] => 10103721 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103721
Semiconductor memory device Mar 24, 2002 Issued
Array ( [id] => 1396081 [patent_doc_number] => 06560142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Capacitorless DRAM gain cell' [patent_app_type] => B1 [patent_app_number] => 10/063119 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2210 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560142.pdf [firstpage_image] =>[orig_patent_app_number] => 10063119 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063119
Capacitorless DRAM gain cell Mar 21, 2002 Issued
Array ( [id] => 1275906 [patent_doc_number] => 06654307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'DDR synchronous flash memory with virtual segment architecture' [patent_app_type] => B2 [patent_app_number] => 10/102757 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6295 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654307.pdf [firstpage_image] =>[orig_patent_app_number] => 10102757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102757
DDR synchronous flash memory with virtual segment architecture Mar 20, 2002 Issued
Array ( [id] => 1238801 [patent_doc_number] => 06690606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Asynchronous interface circuit and method for a pseudo-static memory device' [patent_app_type] => B2 [patent_app_number] => 10/102221 [patent_app_country] => US [patent_app_date] => 2002-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3897 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/690/06690606.pdf [firstpage_image] =>[orig_patent_app_number] => 10102221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102221
Asynchronous interface circuit and method for a pseudo-static memory device Mar 18, 2002 Issued
Array ( [id] => 1419143 [patent_doc_number] => 06535452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Semiconductor memory device having error correction function for data reading during refresh operation' [patent_app_type] => B2 [patent_app_number] => 10/097621 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6625 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535452.pdf [firstpage_image] =>[orig_patent_app_number] => 10097621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097621
Semiconductor memory device having error correction function for data reading during refresh operation Mar 14, 2002 Issued
Array ( [id] => 1256102 [patent_doc_number] => 06671220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Semiconductor device having simplified internal data transfer' [patent_app_type] => B2 [patent_app_number] => 10/096425 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4481 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671220.pdf [firstpage_image] =>[orig_patent_app_number] => 10096425 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/096425
Semiconductor device having simplified internal data transfer Mar 12, 2002 Issued
Array ( [id] => 6014023 [patent_doc_number] => 20020101754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Semiconductor memory device including an SOI' [patent_app_type] => new [patent_app_number] => 10/094918 [patent_app_country] => US [patent_app_date] => 2002-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 64 [patent_no_of_words] => 24403 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20020101754.pdf [firstpage_image] =>[orig_patent_app_number] => 10094918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/094918
Semiconductor memory device including an SOI substrate Mar 11, 2002 Issued
Array ( [id] => 1401964 [patent_doc_number] => 06552934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Apparatus and method for programming voltage protection in a non-volatile memory system' [patent_app_type] => B2 [patent_app_number] => 10/082972 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6925 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552934.pdf [firstpage_image] =>[orig_patent_app_number] => 10082972 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082972
Apparatus and method for programming voltage protection in a non-volatile memory system Feb 25, 2002 Issued
Array ( [id] => 6506518 [patent_doc_number] => 20020135013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Segmented bit line EEPROM page architecture' [patent_app_type] => new [patent_app_number] => 10/082698 [patent_app_country] => US [patent_app_date] => 2002-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6684 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20020135013.pdf [firstpage_image] =>[orig_patent_app_number] => 10082698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082698
Segmented bit line EEPROM page architecture Feb 24, 2002 Issued
Array ( [id] => 1384009 [patent_doc_number] => 06567300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Narrow contact design for magnetic random access memory (MRAM) arrays' [patent_app_type] => B1 [patent_app_number] => 10/080415 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3825 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567300.pdf [firstpage_image] =>[orig_patent_app_number] => 10080415 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080415
Narrow contact design for magnetic random access memory (MRAM) arrays Feb 21, 2002 Issued
Array ( [id] => 1572662 [patent_doc_number] => 06498747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Magnetoresistive random access memory (MRAM) cross-point array with reduced parasitic effects' [patent_app_type] => B1 [patent_app_number] => 10/068913 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3609 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498747.pdf [firstpage_image] =>[orig_patent_app_number] => 10068913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068913
Magnetoresistive random access memory (MRAM) cross-point array with reduced parasitic effects Feb 7, 2002 Issued
Array ( [id] => 6850322 [patent_doc_number] => 20030142524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Methods for saving power and area for content addressable memory devices' [patent_app_type] => new [patent_app_number] => 10/057425 [patent_app_country] => US [patent_app_date] => 2002-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10810 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20030142524.pdf [firstpage_image] =>[orig_patent_app_number] => 10057425 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/057425
Methods for saving power and area for content addressable memory devices Jan 24, 2002 Issued
Array ( [id] => 1108172 [patent_doc_number] => 06813194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Bias distribution network for digital multilevel nonvolatile flash memory' [patent_app_type] => B2 [patent_app_number] => 10/044821 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7225 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813194.pdf [firstpage_image] =>[orig_patent_app_number] => 10044821 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044821
Bias distribution network for digital multilevel nonvolatile flash memory Jan 9, 2002 Issued
Array ( [id] => 1227318 [patent_doc_number] => 06700820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Programming non-volatile memory devices' [patent_app_type] => B2 [patent_app_number] => 10/038119 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3737 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700820.pdf [firstpage_image] =>[orig_patent_app_number] => 10038119 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038119
Programming non-volatile memory devices Jan 2, 2002 Issued
Array ( [id] => 6597173 [patent_doc_number] => 20020085427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Semiconductor memory device for variably controlling drivability' [patent_app_type] => new [patent_app_number] => 10/029947 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1590 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20020085427.pdf [firstpage_image] =>[orig_patent_app_number] => 10029947 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029947
Semiconductor memory device for variably controlling drivability Dec 30, 2001 Issued
Array ( [id] => 1413973 [patent_doc_number] => 06542433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Column address buffering circuit' [patent_app_type] => B2 [patent_app_number] => 10/035733 [patent_app_country] => US [patent_app_date] => 2001-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3676 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542433.pdf [firstpage_image] =>[orig_patent_app_number] => 10035733 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035733
Column address buffering circuit Dec 25, 2001 Issued
Array ( [id] => 6681966 [patent_doc_number] => 20030117830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Ferroelectric memory and method of reading the same' [patent_app_type] => new [patent_app_number] => 10/028519 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5224 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117830.pdf [firstpage_image] =>[orig_patent_app_number] => 10028519 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028519
Ferroelectric memory and method of reading the same Dec 20, 2001 Issued
Array ( [id] => 6682009 [patent_doc_number] => 20030117873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Hysteresis reduced sense amplifier and method of operation' [patent_app_type] => new [patent_app_number] => 10/027547 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117873.pdf [firstpage_image] =>[orig_patent_app_number] => 10027547 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/027547
Hysteresis reduced sense amplifier and method of operation Dec 20, 2001 Issued
Array ( [id] => 6435758 [patent_doc_number] => 20020176301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Virtual static random access memory device and driving method therefor' [patent_app_type] => new [patent_app_number] => 10/025029 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 12806 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20020176301.pdf [firstpage_image] =>[orig_patent_app_number] => 10025029 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/025029
Virtual static random access memory device and driving method therefor Dec 18, 2001 Issued
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