
Amanda T. Le
Examiner (ID: 1115)
| Most Active Art Unit | 2634 |
| Art Unit(s) | 2614, 2634, 2734, 2787 |
| Total Applications | 756 |
| Issued Applications | 614 |
| Pending Applications | 93 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3785287
[patent_doc_number] => 05774498
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Data transmitting apparatus and method of same'
[patent_app_type] => 1
[patent_app_number] => 8/702479
[patent_app_country] => US
[patent_app_date] => 1996-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 50
[patent_no_of_words] => 11489
[patent_no_of_claims] => 31
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[patent_words_short_claim] => 95
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774498.pdf
[firstpage_image] =>[orig_patent_app_number] => 702479
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/702479 | Data transmitting apparatus and method of same | Nov 7, 1996 | Issued |
Array
(
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[patent_doc_number] => 05790609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Apparatus for cleanly switching between various clock sources in a data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/743019
[patent_app_country] => US
[patent_app_date] => 1996-11-04
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[patent_words_short_claim] => 215
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[pdf_file] => patents/05/790/05790609.pdf
[firstpage_image] =>[orig_patent_app_number] => 743019
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/743019 | Apparatus for cleanly switching between various clock sources in a data processing system | Nov 3, 1996 | Issued |
Array
(
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[patent_doc_number] => 05896417
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Apparatus utilizing current-to-voltage conversion for transmitting data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks'
[patent_app_type] => 1
[patent_app_number] => 8/738149
[patent_app_country] => US
[patent_app_date] => 1996-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 12570
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[pdf_file] => patents/05/896/05896417.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/738149 | Apparatus utilizing current-to-voltage conversion for transmitting data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks | Oct 24, 1996 | Issued |
Array
(
[id] => 3875946
[patent_doc_number] => 05793817
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'DC offset reduction in a transmitter'
[patent_app_type] => 1
[patent_app_number] => 8/735629
[patent_app_country] => US
[patent_app_date] => 1996-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4171
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/735629 | DC offset reduction in a transmitter | Oct 22, 1996 | Issued |
Array
(
[id] => 3884678
[patent_doc_number] => 05838744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'High speed modem and method having jitter-free timing recovery'
[patent_app_type] => 1
[patent_app_number] => 8/735139
[patent_app_country] => US
[patent_app_date] => 1996-10-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/838/05838744.pdf
[firstpage_image] =>[orig_patent_app_number] => 735139
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/735139 | High speed modem and method having jitter-free timing recovery | Oct 21, 1996 | Issued |
Array
(
[id] => 3875136
[patent_doc_number] => 05796786
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Phase error detecting method and phase tracking loop circuit'
[patent_app_type] => 1
[patent_app_number] => 8/733569
[patent_app_country] => US
[patent_app_date] => 1996-10-18
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[pdf_file] => patents/05/796/05796786.pdf
[firstpage_image] =>[orig_patent_app_number] => 733569
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/733569 | Phase error detecting method and phase tracking loop circuit | Oct 17, 1996 | Issued |
Array
(
[id] => 3938849
[patent_doc_number] => 05946354
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Hard disk drive read channel with half speed timing'
[patent_app_type] => 1
[patent_app_number] => 8/730862
[patent_app_country] => US
[patent_app_date] => 1996-10-18
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[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/946/05946354.pdf
[firstpage_image] =>[orig_patent_app_number] => 730862
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730862 | Hard disk drive read channel with half speed timing | Oct 17, 1996 | Issued |
Array
(
[id] => 4206268
[patent_doc_number] => 06044123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method and apparatus for fast clock recovery phase-locked loop with training capability'
[patent_app_type] => 1
[patent_app_number] => 8/733869
[patent_app_country] => US
[patent_app_date] => 1996-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4165
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/044/06044123.pdf
[firstpage_image] =>[orig_patent_app_number] => 733869
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/733869 | Method and apparatus for fast clock recovery phase-locked loop with training capability | Oct 16, 1996 | Issued |
Array
(
[id] => 4065434
[patent_doc_number] => 05933450
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Complexity determining apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/722236
[patent_app_country] => US
[patent_app_date] => 1996-10-15
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[firstpage_image] =>[orig_patent_app_number] => 722236
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/722236 | Complexity determining apparatus | Oct 14, 1996 | Issued |
Array
(
[id] => 4198521
[patent_doc_number] => 06094464
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[patent_issue_date] => 2000-07-25
[patent_title] => 'Burst mode receiver'
[patent_app_type] => 1
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[patent_app_date] => 1996-10-11
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[pdf_file] => patents/06/094/06094464.pdf
[firstpage_image] =>[orig_patent_app_number] => 728949
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/728949 | Burst mode receiver | Oct 10, 1996 | Issued |
Array
(
[id] => 4062589
[patent_doc_number] => 05870432
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Method for transmission line impulse response equalization and a device to perform this method'
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[pdf_file] => patents/05/870/05870432.pdf
[firstpage_image] =>[orig_patent_app_number] => 729429
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/729429 | Method for transmission line impulse response equalization and a device to perform this method | Oct 10, 1996 | Issued |
Array
(
[id] => 3884695
[patent_doc_number] => 05838745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Synchronization method, and associated circuitry, for improved synchronization of a receiver with a transmitter using nonlinear transformation metrics'
[patent_app_type] => 1
[patent_app_number] => 8/728179
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[firstpage_image] =>[orig_patent_app_number] => 728179
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Array
(
[id] => 4020964
[patent_doc_number] => 05889820
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'SPDIF-AES/EBU digital audio data recovery'
[patent_app_type] => 1
[patent_app_number] => 8/727020
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[firstpage_image] =>[orig_patent_app_number] => 727020
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/727020 | SPDIF-AES/EBU digital audio data recovery | Oct 7, 1996 | Issued |
Array
(
[id] => 3891424
[patent_doc_number] => 05729574
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[patent_issue_date] => 1998-03-17
[patent_title] => 'Single channel FIR filter architecture to perform combined/parallel filtering of multiple (quadrature) signals'
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Array
(
[id] => 3894142
[patent_doc_number] => 05805636
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[patent_title] => 'Method and apparatus for simultaneous voice, data, and video communication in a computer system'
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Array
(
[id] => 4062704
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Array
(
[id] => 3941304
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[patent_title] => 'Method and apparatus for producing a deterministic sequence from an IIR filter'
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Array
(
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Array
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 711908
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/711908 | Delay stage circuitry for a ring oscillator | Sep 11, 1996 | Issued |