Search

Amanda T. Le

Examiner (ID: 1115)

Most Active Art Unit
2634
Art Unit(s)
2614, 2634, 2734, 2787
Total Applications
756
Issued Applications
614
Pending Applications
93
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3785287 [patent_doc_number] => 05774498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Data transmitting apparatus and method of same' [patent_app_type] => 1 [patent_app_number] => 8/702479 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 50 [patent_no_of_words] => 11489 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774498.pdf [firstpage_image] =>[orig_patent_app_number] => 702479 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702479
Data transmitting apparatus and method of same Nov 7, 1996 Issued
Array ( [id] => 3832951 [patent_doc_number] => 05790609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Apparatus for cleanly switching between various clock sources in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/743019 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5397 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790609.pdf [firstpage_image] =>[orig_patent_app_number] => 743019 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743019
Apparatus for cleanly switching between various clock sources in a data processing system Nov 3, 1996 Issued
Array ( [id] => 4074705 [patent_doc_number] => 05896417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Apparatus utilizing current-to-voltage conversion for transmitting data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks' [patent_app_type] => 1 [patent_app_number] => 8/738149 [patent_app_country] => US [patent_app_date] => 1996-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12570 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896417.pdf [firstpage_image] =>[orig_patent_app_number] => 738149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738149
Apparatus utilizing current-to-voltage conversion for transmitting data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks Oct 24, 1996 Issued
Array ( [id] => 3875946 [patent_doc_number] => 05793817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'DC offset reduction in a transmitter' [patent_app_type] => 1 [patent_app_number] => 8/735629 [patent_app_country] => US [patent_app_date] => 1996-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4171 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793817.pdf [firstpage_image] =>[orig_patent_app_number] => 735629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735629
DC offset reduction in a transmitter Oct 22, 1996 Issued
Array ( [id] => 3884678 [patent_doc_number] => 05838744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'High speed modem and method having jitter-free timing recovery' [patent_app_type] => 1 [patent_app_number] => 8/735139 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5836 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838744.pdf [firstpage_image] =>[orig_patent_app_number] => 735139 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735139
High speed modem and method having jitter-free timing recovery Oct 21, 1996 Issued
Array ( [id] => 3875136 [patent_doc_number] => 05796786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Phase error detecting method and phase tracking loop circuit' [patent_app_type] => 1 [patent_app_number] => 8/733569 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796786.pdf [firstpage_image] =>[orig_patent_app_number] => 733569 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733569
Phase error detecting method and phase tracking loop circuit Oct 17, 1996 Issued
Array ( [id] => 3938849 [patent_doc_number] => 05946354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Hard disk drive read channel with half speed timing' [patent_app_type] => 1 [patent_app_number] => 8/730862 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3132 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946354.pdf [firstpage_image] =>[orig_patent_app_number] => 730862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730862
Hard disk drive read channel with half speed timing Oct 17, 1996 Issued
Array ( [id] => 4206268 [patent_doc_number] => 06044123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Method and apparatus for fast clock recovery phase-locked loop with training capability' [patent_app_type] => 1 [patent_app_number] => 8/733869 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4165 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044123.pdf [firstpage_image] =>[orig_patent_app_number] => 733869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733869
Method and apparatus for fast clock recovery phase-locked loop with training capability Oct 16, 1996 Issued
Array ( [id] => 4065434 [patent_doc_number] => 05933450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Complexity determining apparatus' [patent_app_type] => 1 [patent_app_number] => 8/722236 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933450.pdf [firstpage_image] =>[orig_patent_app_number] => 722236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/722236
Complexity determining apparatus Oct 14, 1996 Issued
Array ( [id] => 4198521 [patent_doc_number] => 06094464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Burst mode receiver' [patent_app_type] => 1 [patent_app_number] => 8/728949 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8147 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094464.pdf [firstpage_image] =>[orig_patent_app_number] => 728949 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/728949
Burst mode receiver Oct 10, 1996 Issued
Array ( [id] => 4062589 [patent_doc_number] => 05870432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method for transmission line impulse response equalization and a device to perform this method' [patent_app_type] => 1 [patent_app_number] => 8/729429 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7908 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870432.pdf [firstpage_image] =>[orig_patent_app_number] => 729429 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729429
Method for transmission line impulse response equalization and a device to perform this method Oct 10, 1996 Issued
Array ( [id] => 3884695 [patent_doc_number] => 05838745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Synchronization method, and associated circuitry, for improved synchronization of a receiver with a transmitter using nonlinear transformation metrics' [patent_app_type] => 1 [patent_app_number] => 8/728179 [patent_app_country] => US [patent_app_date] => 1996-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4909 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838745.pdf [firstpage_image] =>[orig_patent_app_number] => 728179 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/728179
Synchronization method, and associated circuitry, for improved synchronization of a receiver with a transmitter using nonlinear transformation metrics Oct 8, 1996 Issued
Array ( [id] => 4020964 [patent_doc_number] => 05889820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'SPDIF-AES/EBU digital audio data recovery' [patent_app_type] => 1 [patent_app_number] => 8/727020 [patent_app_country] => US [patent_app_date] => 1996-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5749 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889820.pdf [firstpage_image] =>[orig_patent_app_number] => 727020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727020
SPDIF-AES/EBU digital audio data recovery Oct 7, 1996 Issued
Array ( [id] => 3891424 [patent_doc_number] => 05729574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Single channel FIR filter architecture to perform combined/parallel filtering of multiple (quadrature) signals' [patent_app_type] => 1 [patent_app_number] => 8/727349 [patent_app_country] => US [patent_app_date] => 1996-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2278 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729574.pdf [firstpage_image] =>[orig_patent_app_number] => 727349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727349
Single channel FIR filter architecture to perform combined/parallel filtering of multiple (quadrature) signals Oct 7, 1996 Issued
Array ( [id] => 3894142 [patent_doc_number] => 05805636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method and apparatus for simultaneous voice, data, and video communication in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/724209 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4825 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805636.pdf [firstpage_image] =>[orig_patent_app_number] => 724209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724209
Method and apparatus for simultaneous voice, data, and video communication in a computer system Sep 30, 1996 Issued
Array ( [id] => 4062704 [patent_doc_number] => 05870438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Fast resynchronization system for high-speed data transmission' [patent_app_type] => 1 [patent_app_number] => 8/721149 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2844 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870438.pdf [firstpage_image] =>[orig_patent_app_number] => 721149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721149
Fast resynchronization system for high-speed data transmission Sep 25, 1996 Issued
Array ( [id] => 3941304 [patent_doc_number] => 05878086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method and apparatus for producing a deterministic sequence from an IIR filter' [patent_app_type] => 1 [patent_app_number] => 8/715949 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3027 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878086.pdf [firstpage_image] =>[orig_patent_app_number] => 715949 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/715949
Method and apparatus for producing a deterministic sequence from an IIR filter Sep 18, 1996 Issued
Array ( [id] => 4074862 [patent_doc_number] => 05896428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Digital counter and digital phase locked loop circuit using same' [patent_app_type] => 1 [patent_app_number] => 8/714275 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4704 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896428.pdf [firstpage_image] =>[orig_patent_app_number] => 714275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714275
Digital counter and digital phase locked loop circuit using same Sep 16, 1996 Issued
Array ( [id] => 4006603 [patent_doc_number] => 05920600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Bit phase synchronizing circuitry for controlling phase and frequency, and PLL circuit therefor' [patent_app_type] => 1 [patent_app_number] => 8/714269 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 188 [patent_no_of_words] => 19090 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920600.pdf [firstpage_image] =>[orig_patent_app_number] => 714269 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714269
Bit phase synchronizing circuitry for controlling phase and frequency, and PLL circuit therefor Sep 16, 1996 Issued
Array ( [id] => 3892990 [patent_doc_number] => 05799051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Delay stage circuitry for a ring oscillator' [patent_app_type] => 1 [patent_app_number] => 8/711908 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9082 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799051.pdf [firstpage_image] =>[orig_patent_app_number] => 711908 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711908
Delay stage circuitry for a ring oscillator Sep 11, 1996 Issued
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