Search

Amarnauth G. Persaud

Examiner (ID: 11557, Phone: (571)270-7295 , Office: P/2477 )

Most Active Art Unit
2477
Art Unit(s)
2477, 2419
Total Applications
440
Issued Applications
365
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18721256 [patent_doc_number] => 11798608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Techniques to perform a sense operation [patent_app_type] => utility [patent_app_number] => 17/646259 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13510 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646259
Techniques to perform a sense operation Dec 27, 2021 Issued
Array ( [id] => 17917161 [patent_doc_number] => 20220319557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => Low Power Scheme for Power Down in Integrated Dual Rail SRAMs [patent_app_type] => utility [patent_app_number] => 17/549962 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549962
Low power scheme for power down in integrated dual rail SRAMs Dec 13, 2021 Issued
Array ( [id] => 18607866 [patent_doc_number] => 11749342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Passive compensation for electrical distance [patent_app_type] => utility [patent_app_number] => 17/549390 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549390
Passive compensation for electrical distance Dec 12, 2021 Issued
Array ( [id] => 18080739 [patent_doc_number] => 20220406351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/643499 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643499
Semiconductor memory device for reducing effect of leakage current Dec 8, 2021 Issued
Array ( [id] => 18828909 [patent_doc_number] => 11844210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Storage device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/542429 [patent_app_country] => US [patent_app_date] => 2021-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542429
Storage device and manufacturing method thereof Dec 4, 2021 Issued
Array ( [id] => 18281144 [patent_doc_number] => 20230096616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => STORAGE DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/542427 [patent_app_country] => US [patent_app_date] => 2021-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542427
Storage device and manufacturing method thereof Dec 4, 2021 Issued
Array ( [id] => 19444256 [patent_doc_number] => 12094542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Device and method to generate bias voltages in non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/542323 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7794 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542323
Device and method to generate bias voltages in non-volatile memory Dec 2, 2021 Issued
Array ( [id] => 17630312 [patent_doc_number] => 20220165327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => INTERFACE OF A MEMORY CIRCUIT AND MEMORY SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 17/529709 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529709
Interface of a memory circuit and memory system thereof Nov 17, 2021 Issued
Array ( [id] => 17795293 [patent_doc_number] => 20220254385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => POWER RAMPING SEQUENCE CONTROL FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/522556 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522556
Power ramping sequence control for a memory device Nov 8, 2021 Issued
Array ( [id] => 18346327 [patent_doc_number] => 20230134437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => TWO-TERMINAL ONE-TIME PROGRAMMABLE FUSES FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/518937 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518937
Two-terminal one-time programmable fuses for memory cells Nov 3, 2021 Issued
Array ( [id] => 17551329 [patent_doc_number] => 20220122671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => METHOD FOR PROGRAMMING CHARGE TRAP FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/506036 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506036
Method for programming charge trap flash memory Oct 19, 2021 Issued
Array ( [id] => 18357664 [patent_doc_number] => 11646070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Memory cell sensing using an averaged reference voltage [patent_app_type] => utility [patent_app_number] => 17/499492 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15785 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499492
Memory cell sensing using an averaged reference voltage Oct 11, 2021 Issued
Array ( [id] => 18623548 [patent_doc_number] => 11756601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Differential sensing for a memory device [patent_app_type] => utility [patent_app_number] => 17/499322 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 19887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499322
Differential sensing for a memory device Oct 11, 2021 Issued
Array ( [id] => 17359634 [patent_doc_number] => 20220020430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => MEMORY OPERATION WITH DOUBLE-SIDED ASYMMETRIC DECODERS [patent_app_type] => utility [patent_app_number] => 17/491070 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491070
Memory operation with double-sided asymmetric decoders Sep 29, 2021 Issued
Array ( [id] => 18639256 [patent_doc_number] => 11763872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => 3D memory array clusters and resulting memory architecture [patent_app_type] => utility [patent_app_number] => 17/488148 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3899 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488148 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488148
3D memory array clusters and resulting memory architecture Sep 27, 2021 Issued
Array ( [id] => 18088381 [patent_doc_number] => 11538520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Negative-capacitance ferroelectric transistor assisted resistive memory programming [patent_app_type] => utility [patent_app_number] => 17/482491 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 8850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482491
Negative-capacitance ferroelectric transistor assisted resistive memory programming Sep 22, 2021 Issued
Array ( [id] => 17339213 [patent_doc_number] => 20220005544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => REPAIR CIRCUIT, MEMORY, AND REPAIR METHOD [patent_app_type] => utility [patent_app_number] => 17/477769 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477769
Repair circuit, memory, and repair method Sep 16, 2021 Issued
Array ( [id] => 17886162 [patent_doc_number] => 20220301639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR CIRCUIT, RECEIVING DEVICE, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/473269 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473269 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473269
Semiconductor circuit, receiving device, and memory system Sep 12, 2021 Issued
Array ( [id] => 18528520 [patent_doc_number] => 11715518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Dynamic inhibit voltage to reduce write power for random-access memory [patent_app_type] => utility [patent_app_number] => 17/470849 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8049 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470849
Dynamic inhibit voltage to reduce write power for random-access memory Sep 8, 2021 Issued
Array ( [id] => 18088368 [patent_doc_number] => 11538507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Header circuit placement in memory device [patent_app_type] => utility [patent_app_number] => 17/461210 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461210
Header circuit placement in memory device Aug 29, 2021 Issued
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