Search

Amarnauth G. Persaud

Examiner (ID: 14863, Phone: (571)270-7295 , Office: P/2477 )

Most Active Art Unit
2477
Art Unit(s)
2419, 2477
Total Applications
440
Issued Applications
365
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20234283 [patent_doc_number] => 20250291602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => EFFICIENT EXECUTION OF ATOMIC INSTRUCTIONS FOR SINGLE INSTRUCTION, MULTIPLE THREAD (SIMT) ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/604201 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604201
EFFICIENT EXECUTION OF ATOMIC INSTRUCTIONS FOR SINGLE INSTRUCTION, MULTIPLE THREAD (SIMT) ARCHITECTURES Mar 12, 2024 Pending
Array ( [id] => 20208653 [patent_doc_number] => 20250278373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => Peripheral Device with Relaxed-Order Bus Interface [patent_app_type] => utility [patent_app_number] => 18/591008 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591008
Peripheral Device with Relaxed-Order Bus Interface Feb 28, 2024 Pending
Array ( [id] => 19334437 [patent_doc_number] => 20240248867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Method for Operating a Field Device of Process Measurement Technology and Filling System with which the Method is Carried Out [patent_app_type] => utility [patent_app_number] => 18/421650 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421650 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421650
Method for operating a field device of process measurement technology and filling system with which the method is carried out Jan 23, 2024 Issued
Array ( [id] => 19334437 [patent_doc_number] => 20240248867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Method for Operating a Field Device of Process Measurement Technology and Filling System with which the Method is Carried Out [patent_app_type] => utility [patent_app_number] => 18/421650 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421650 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421650
Method for operating a field device of process measurement technology and filling system with which the method is carried out Jan 23, 2024 Issued
Array ( [id] => 20160141 [patent_doc_number] => 12386770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Interface bus combining [patent_app_type] => utility [patent_app_number] => 18/420431 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420431
Interface bus combining Jan 22, 2024 Issued
Array ( [id] => 20160141 [patent_doc_number] => 12386770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Interface bus combining [patent_app_type] => utility [patent_app_number] => 18/420431 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420431
Interface bus combining Jan 22, 2024 Issued
Array ( [id] => 20358737 [patent_doc_number] => 12474730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Deserializer and memory module including the same [patent_app_type] => utility [patent_app_number] => 18/418856 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418856
Deserializer and memory module including the same Jan 21, 2024 Issued
Array ( [id] => 20358737 [patent_doc_number] => 12474730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Deserializer and memory module including the same [patent_app_type] => utility [patent_app_number] => 18/418856 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418856
Deserializer and memory module including the same Jan 21, 2024 Issued
Array ( [id] => 19159779 [patent_doc_number] => 20240152486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Reconfigurable Processor Circuit Architecture [patent_app_type] => utility [patent_app_number] => 18/415958 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415958 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415958
Reconfigurable processor circuit architecture Jan 17, 2024 Issued
Array ( [id] => 19159779 [patent_doc_number] => 20240152486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Reconfigurable Processor Circuit Architecture [patent_app_type] => utility [patent_app_number] => 18/415958 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415958 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415958
Reconfigurable processor circuit architecture Jan 17, 2024 Issued
Array ( [id] => 20101830 [patent_doc_number] => 20250231766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => REGISTER ACCESS VIA A READ PORT [patent_app_type] => utility [patent_app_number] => 18/410534 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410534 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410534
Register access via a read port Jan 10, 2024 Issued
Array ( [id] => 19303242 [patent_doc_number] => 20240231822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => CONTROL METHOD AND CHIP [patent_app_type] => utility [patent_app_number] => 18/408047 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408047
CONTROL METHOD AND CHIP Jan 8, 2024 Pending
Array ( [id] => 19129292 [patent_doc_number] => 20240134645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP [patent_app_type] => utility [patent_app_number] => 18/402519 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 58433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402519
USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP Jan 1, 2024 Pending
Array ( [id] => 20070653 [patent_doc_number] => 20250208875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => LOAD FUSION [patent_app_type] => utility [patent_app_number] => 18/392187 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/392187
LOAD FUSION Dec 20, 2023 Pending
Array ( [id] => 20070653 [patent_doc_number] => 20250208875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => LOAD FUSION [patent_app_type] => utility [patent_app_number] => 18/392187 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/392187
LOAD FUSION Dec 20, 2023 Pending
Array ( [id] => 19235913 [patent_doc_number] => 20240193108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE [patent_app_type] => utility [patent_app_number] => 18/545189 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545189
HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE Dec 18, 2023 Pending
Array ( [id] => 19235913 [patent_doc_number] => 20240193108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE [patent_app_type] => utility [patent_app_number] => 18/545189 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545189
HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE Dec 18, 2023 Pending
Array ( [id] => 19129297 [patent_doc_number] => 20240134650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => DEVICES TRANSFERRING CACHE LINES, INCLUDING METADATA ON EXTERNAL LINKS [patent_app_type] => utility [patent_app_number] => 18/545603 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545603
Devices transferring cache lines, including metadata on external links Dec 18, 2023 Issued
Array ( [id] => 19514183 [patent_doc_number] => 20240345869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/541670 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/541670
SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR Dec 14, 2023 Issued
Array ( [id] => 19514183 [patent_doc_number] => 20240345869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/541670 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/541670
SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR Dec 14, 2023 Issued
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