Search

Amarnauth G. Persaud

Examiner (ID: 11557, Phone: (571)270-7295 , Office: P/2477 )

Most Active Art Unit
2477
Art Unit(s)
2477, 2419
Total Applications
440
Issued Applications
365
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18905765 [patent_doc_number] => 20240021250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/362221 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362221 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362221
Memory system Jul 30, 2023 Issued
Array ( [id] => 19712349 [patent_doc_number] => 20250022491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SYSTEM FOR SAVING LEAKAGE POWER IN STATIC RANDOM ACCESS MEMORY (SRAM) USING LIGHT SLEEP MODE [patent_app_type] => utility [patent_app_number] => 18/352625 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352625
SYSTEM FOR SAVING LEAKAGE POWER IN STATIC RANDOM ACCESS MEMORY (SRAM) USING LIGHT SLEEP MODE Jul 13, 2023 Abandoned
Array ( [id] => 18729097 [patent_doc_number] => 20230343392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating [patent_app_type] => utility [patent_app_number] => 18/214714 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/214714
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating Jun 26, 2023 Issued
Array ( [id] => 19523014 [patent_doc_number] => 12124741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Memory module interfaces [patent_app_type] => utility [patent_app_number] => 18/340589 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340589 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340589
Memory module interfaces Jun 22, 2023 Issued
Array ( [id] => 18712557 [patent_doc_number] => 20230335190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => REDUCING DISTURBANCE IN CROSSBAR ARRAY CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/336814 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336814 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336814
Reducing disturbance in crossbar array circuits Jun 15, 2023 Issued
Array ( [id] => 18712556 [patent_doc_number] => 20230335189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => NOVEL DYNAMIC INHIBIT VOLTAGE TO REDUCE WRITE POWER FOR RANDOM-ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/336395 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336395
Dynamic inhibit voltage to reduce write power for random-access memory Jun 15, 2023 Issued
Array ( [id] => 19646228 [patent_doc_number] => 20240420748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SHARED METAL WIRE CAPACITANCE FOR NEGATIVE BIT-LINE [patent_app_type] => utility [patent_app_number] => 18/336758 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336758
Shared metal wire capacitance for negative bit-line Jun 15, 2023 Issued
Array ( [id] => 18696061 [patent_doc_number] => 20230326492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => Low Power Scheme for Power Down in Integrated Dual Rail SRAMs [patent_app_type] => utility [patent_app_number] => 18/328836 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328836
Low Power Scheme for Power Down in Integrated Dual Rail SRAMs Jun 4, 2023 Pending
Array ( [id] => 19610785 [patent_doc_number] => 12159665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Method of programming memory device and related memory device [patent_app_type] => utility [patent_app_number] => 18/204266 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204266
Method of programming memory device and related memory device May 30, 2023 Issued
Array ( [id] => 20455755 [patent_doc_number] => 12518815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Systems and methods for a power wake-up sequence in a memory device [patent_app_type] => utility [patent_app_number] => 18/326057 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326057
Systems and methods for a power wake-up sequence in a memory device May 30, 2023 Issued
Array ( [id] => 18864306 [patent_doc_number] => 20230418742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => OUT-OF-ORDER PROGRAMMING OF FIRST WORDLINE IN A PHYSICAL UNIT OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/203223 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203223 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203223
Out-of-order programming of first wordline in a physical unit of a memory device May 29, 2023 Issued
Array ( [id] => 18585732 [patent_doc_number] => 20230267996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => Self-Selecting Memory Cells Configured to Store More Than One Bit per Memory Cell [patent_app_type] => utility [patent_app_number] => 18/310736 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310736 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310736
Self-Selecting Memory Cells Configured to Store More Than One Bit per Memory Cell May 1, 2023 Pending
Array ( [id] => 18555025 [patent_doc_number] => 20230253041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => MEMORY CELL ARRAY CIRCUIT AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/304297 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304297 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304297
Memory cell array circuit and method of forming the same Apr 19, 2023 Issued
Array ( [id] => 20102865 [patent_doc_number] => 20250232801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY CONTROL DEVICE [patent_app_type] => utility [patent_app_number] => 18/849180 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18849180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/849180
MEMORY CONTROL DEVICE Mar 8, 2023 Pending
Array ( [id] => 18631512 [patent_doc_number] => 20230290414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => MEMORY CELL AND ARRAY STRUCTURE OF NON-VOLATILE MEMORY AND ASSOCIATED CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/113675 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113675 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113675
Memory cell and array structure of non-volatile memory and associated control method Feb 23, 2023 Issued
Array ( [id] => 18408663 [patent_doc_number] => 20230170016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => MEMORY ARRAY STRUCTURES AND METHODS OF FORMING MEMORY ARRAY STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/096072 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096072
Memory array structures and methods of forming memory array structures Jan 11, 2023 Issued
Array ( [id] => 18532966 [patent_doc_number] => 20230238041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => MEMORY AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES [patent_app_type] => utility [patent_app_number] => 18/089668 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089668
Memory and system supporting parallel and serial access modes Dec 27, 2022 Issued
Array ( [id] => 19016094 [patent_doc_number] => 11923034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Header circuit placement in memory device [patent_app_type] => utility [patent_app_number] => 18/088216 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088216 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088216
Header circuit placement in memory device Dec 22, 2022 Issued
Array ( [id] => 20080592 [patent_doc_number] => 12354667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor device and programming method capable of programming with reduced power consumption [patent_app_type] => utility [patent_app_number] => 18/080752 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080752 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080752
Semiconductor device and programming method capable of programming with reduced power consumption Dec 13, 2022 Issued
Array ( [id] => 19414538 [patent_doc_number] => 12080372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => System and method of power management in memory design [patent_app_type] => utility [patent_app_number] => 18/064048 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064048 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064048
System and method of power management in memory design Dec 8, 2022 Issued
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