Search

Amber D. Steele

Examiner (ID: 5727, Phone: (571)272-5538 , Office: P/1676 )

Most Active Art Unit
1658
Art Unit(s)
1676, 1639, 1654, 1658
Total Applications
1273
Issued Applications
621
Pending Applications
157
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19773095 [patent_doc_number] => 20250054521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/928444 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/928444
SEMICONDUCTOR DEVICE Oct 27, 2024 Pending
Array ( [id] => 20071850 [patent_doc_number] => 20250210072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => BITLINE SENSING AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/883399 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883399
BITLINE SENSING AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME Sep 11, 2024 Pending
Array ( [id] => 20572051 [patent_doc_number] => 20260065979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => BIT LINE CHARGE SHARING FOR SRAM DYNAMIC POWER SAVINGS [patent_app_type] => utility [patent_app_number] => 18/823460 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823460
BIT LINE CHARGE SHARING FOR SRAM DYNAMIC POWER SAVINGS Sep 2, 2024 Pending
Array ( [id] => 19820731 [patent_doc_number] => 20250078938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/823541 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823541
VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE Sep 2, 2024 Pending
Array ( [id] => 19850412 [patent_doc_number] => 20250095763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => TEST APPARATUS AND TEST METHOD [patent_app_type] => utility [patent_app_number] => 18/814460 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814460
TEST APPARATUS AND TEST METHOD Aug 22, 2024 Pending
Array ( [id] => 20071870 [patent_doc_number] => 20250210092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/797883 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797883
INTEGRATED CIRCUIT DEVICE Aug 7, 2024 Pending
Array ( [id] => 20475980 [patent_doc_number] => 20260018201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => Pulse Signal Generator System for a Magnetoresistive Random Access Memory Array [patent_app_type] => utility [patent_app_number] => 18/789717 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789717
Pulse signal generator system for a magnetoresistive random access memory array Jul 30, 2024 Issued
Array ( [id] => 20010853 [patent_doc_number] => 20250149075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 18/788898 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788898
SEMICONDUCTOR DEVICE AND MEMORY MODULE Jul 29, 2024 Pending
Array ( [id] => 19773111 [patent_doc_number] => 20250054537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM TO BALANCE GROUND BOUNCE [patent_app_type] => utility [patent_app_number] => 18/788879 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788879
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE Jul 29, 2024 Pending
Array ( [id] => 20198781 [patent_doc_number] => 20250275491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => Three-Dimensional Structure of Polarity Memory Chalcogenide [patent_app_type] => utility [patent_app_number] => 18/781354 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781354 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781354
Three-Dimensional Structure of Polarity Memory Chalcogenide Jul 22, 2024 Pending
Array ( [id] => 19559626 [patent_doc_number] => 20240371418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/772714 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772714
Circuits and methods of mitigating hold time failure of pipeline for memory device Jul 14, 2024 Issued
Array ( [id] => 20235509 [patent_doc_number] => 20250292828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => METHOD, DEVICE, AND CIRCUIT FOR MEMORIES FOR SKIPPING PRE-CHARGING [patent_app_type] => utility [patent_app_number] => 18/769678 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769678
METHOD, DEVICE, AND CIRCUIT FOR MEMORIES FOR SKIPPING PRE-CHARGING Jul 10, 2024 Pending
Array ( [id] => 19546123 [patent_doc_number] => 20240363159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/769120 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769120
MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD Jul 9, 2024 Pending
Array ( [id] => 19661770 [patent_doc_number] => 20240428835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING [patent_app_type] => utility [patent_app_number] => 18/767988 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767988 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767988
SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING Jul 9, 2024 Pending
Array ( [id] => 19696109 [patent_doc_number] => 20250014654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/758496 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758496
ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICE Jun 27, 2024 Pending
Array ( [id] => 20624752 [patent_doc_number] => 12592264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Reduction in chip area through design-technology co-optimization [patent_app_type] => utility [patent_app_number] => 18/758643 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 15633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758643
Reduction in chip area through design-technology co-optimization Jun 27, 2024 Issued
Array ( [id] => 19993733 [patent_doc_number] => 20250131955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => APPARATUSES AND METHODS FOR ROW HAMMER COUNTER INITIALIZATION [patent_app_type] => utility [patent_app_number] => 18/756919 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756919
APPARATUSES AND METHODS FOR ROW HAMMER COUNTER INITIALIZATION Jun 26, 2024 Pending
Array ( [id] => 19788257 [patent_doc_number] => 20250061936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/754884 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754884
MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS Jun 25, 2024 Pending
Array ( [id] => 19515433 [patent_doc_number] => 20240347119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/753717 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753717
MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES Jun 24, 2024 Pending
Array ( [id] => 20214954 [patent_doc_number] => 12411606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => High capacity memory circuit with low effective latency [patent_app_type] => utility [patent_app_number] => 18/750979 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 9805 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750979 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750979
High capacity memory circuit with low effective latency Jun 20, 2024 Issued
Menu