Search

Amber D. Steele

Examiner (ID: 5727, Phone: (571)272-5538 , Office: P/1676 )

Most Active Art Unit
1658
Art Unit(s)
1676, 1639, 1654, 1658
Total Applications
1273
Issued Applications
621
Pending Applications
157
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16826398 [patent_doc_number] => 20210141691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/091826 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/091826
Semiconductor devices and semiconductor systems including the same Nov 5, 2020 Issued
Array ( [id] => 17448703 [patent_doc_number] => 20220069208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR INITIALIZING THE SAME [patent_app_type] => utility [patent_app_number] => 17/088736 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088736
RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR INITIALIZING THE SAME Nov 3, 2020 Abandoned
Array ( [id] => 17581349 [patent_doc_number] => 20220138204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => ACCELERATING CONSTRAINED, FLEXIBLE, AND OPTIMIZABLE RULE LOOK-UPS IN HARDWARE [patent_app_type] => utility [patent_app_number] => 17/085805 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085805
Accelerating constrained, flexible, and optimizable rule look-ups in hardware Oct 29, 2020 Issued
Array ( [id] => 17698823 [patent_doc_number] => 11372545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Managing bin placement for block families of a memory device based on trigger metric values [patent_app_type] => utility [patent_app_number] => 17/084549 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084549
Managing bin placement for block families of a memory device based on trigger metric values Oct 28, 2020 Issued
Array ( [id] => 17410025 [patent_doc_number] => 11250921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Programming and verifying method for multilevel memory cell array [patent_app_type] => utility [patent_app_number] => 17/069889 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7653 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069889
Programming and verifying method for multilevel memory cell array Oct 13, 2020 Issued
Array ( [id] => 17730840 [patent_doc_number] => 11387242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Non-volatile memory (NVM) cell structure to increase reliability [patent_app_type] => utility [patent_app_number] => 17/068924 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 14287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068924
Non-volatile memory (NVM) cell structure to increase reliability Oct 12, 2020 Issued
Array ( [id] => 16723522 [patent_doc_number] => 20210090669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => INTRA-CODE WORD WEAR LEVELING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/066399 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066399 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066399
Intra-code word wear leveling techniques Oct 7, 2020 Issued
Array ( [id] => 16730232 [patent_doc_number] => 20210097379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => CIRCUIT FOR CALCULATING WEIGHT ADJUSTMENTS OF AN ARTIFICIAL NEURAL NETWORK, AND A MODULE IMPLEMENTING A LONG SHORT-TERM ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/033777 [patent_app_country] => US [patent_app_date] => 2020-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033777
Circuit for calculating weight adjustments of an artificial neural network, and a module implementing a long short-term artificial neural network Sep 25, 2020 Issued
Array ( [id] => 16544690 [patent_doc_number] => 20200411105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => NON-VOLATILE MEMORY DEVICE AND ERASING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/019889 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019889
Non-volatile memory device and erasing method of the same Sep 13, 2020 Issued
Array ( [id] => 16544647 [patent_doc_number] => 20200411062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => High Bandwidth Memory Having Plural Channels [patent_app_type] => utility [patent_app_number] => 17/020712 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020712
High bandwidth memory having plural channels Sep 13, 2020 Issued
Array ( [id] => 16965977 [patent_doc_number] => 20210217476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/018034 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018034
Memory system Sep 10, 2020 Issued
Array ( [id] => 16544653 [patent_doc_number] => 20200411068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => POWER MANAGEMENT INTEGRATED CIRCUIT WITH DUAL POWER FEED [patent_app_type] => utility [patent_app_number] => 17/018051 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018051
Power management integrated circuit with dual power feed Sep 10, 2020 Issued
Array ( [id] => 17475959 [patent_doc_number] => 20220083463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => MANAGING WORKLOAD OF PROGRAMMING SETS OF PAGES TO MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/948302 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948302
Managing workload of programming sets of pages to memory device Sep 10, 2020 Issued
Array ( [id] => 16544666 [patent_doc_number] => 20200411081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => MEMORY WITH ON-DIE DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 17/017545 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017545
Memory with on-die data transfer Sep 9, 2020 Issued
Array ( [id] => 17099937 [patent_doc_number] => 20210287728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/016256 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/016256
Memory device Sep 8, 2020 Issued
Array ( [id] => 17559173 [patent_doc_number] => 11315895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Semiconductor memory device having wafer-to-wafer bonding structure [patent_app_type] => utility [patent_app_number] => 17/014349 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12294 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014349
Semiconductor memory device having wafer-to-wafer bonding structure Sep 7, 2020 Issued
Array ( [id] => 17438762 [patent_doc_number] => 11264102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/007896 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 12166 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007896 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007896
Semiconductor storage device Aug 30, 2020 Issued
Array ( [id] => 17010676 [patent_doc_number] => 20210241837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/007691 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007691
Semiconductor memory device Aug 30, 2020 Issued
Array ( [id] => 19016083 [patent_doc_number] => 11923023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Debug capabilities of a memory system with a pin [patent_app_type] => utility [patent_app_number] => 16/982912 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10758 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16982912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/982912
Debug capabilities of a memory system with a pin Aug 30, 2020 Issued
Array ( [id] => 16515813 [patent_doc_number] => 20200395071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => METHODS FOR PROGRAMING DDR COMPATIBLE OPEN ARCHITECTURE RESISTIVE CHANGE ELEMENT ARRAYS [patent_app_type] => utility [patent_app_number] => 17/007735 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 71149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007735 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007735
Methods for programing DDR compatible open architecture resistive change element arrays Aug 30, 2020 Issued
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