Search

Amber D. Steele

Examiner (ID: 5727, Phone: (571)272-5538 , Office: P/1676 )

Most Active Art Unit
1658
Art Unit(s)
1676, 1639, 1654, 1658
Total Applications
1273
Issued Applications
621
Pending Applications
157
Abandoned Applications
533

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18989623 [patent_doc_number] => 20240061592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => MULTIPLE CURRENT QUANTIZATION VALUES FOR PEAK POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/231338 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231338
Multiple current quantization values for peak power management Aug 7, 2023 Issued
Array ( [id] => 19686115 [patent_doc_number] => 20250004660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SOLID-STATE DRIVE SECURE DATA WIPING FOR REUSE AND RECYCLING [patent_app_type] => utility [patent_app_number] => 18/230145 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230145
Solid-state drive secure data wiping for reuse and recycling Aug 2, 2023 Issued
Array ( [id] => 20161151 [patent_doc_number] => 12387784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory circuit [patent_app_type] => utility [patent_app_number] => 18/229182 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229182 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229182
Memory circuit Aug 1, 2023 Issued
Array ( [id] => 19434482 [patent_doc_number] => 20240302980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/363251 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363251 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363251
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME Jul 31, 2023 Issued
Array ( [id] => 20609791 [patent_doc_number] => 12585393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Low power and area optimized TM4 and TM5 compliant combination TMIO transmitter architecture [patent_app_type] => utility [patent_app_number] => 18/354211 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 12178 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354211 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354211
Low power and area optimized TM4 and TM5 compliant combination TMIO transmitter architecture Jul 17, 2023 Issued
Array ( [id] => 20434890 [patent_doc_number] => 12505872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Apparatuses and methods for generating clock signals [patent_app_type] => utility [patent_app_number] => 18/353607 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3636 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353607
Apparatuses and methods for generating clock signals Jul 16, 2023 Issued
Array ( [id] => 19627238 [patent_doc_number] => 12166089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Method of manufacturing semiconductor device and associated memory device [patent_app_type] => utility [patent_app_number] => 18/352289 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352289
Method of manufacturing semiconductor device and associated memory device Jul 13, 2023 Issued
Array ( [id] => 19610789 [patent_doc_number] => 12159669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating [patent_app_type] => utility [patent_app_number] => 18/221330 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 75 [patent_no_of_words] => 22914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221330 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221330
Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating Jul 11, 2023 Issued
Array ( [id] => 19711088 [patent_doc_number] => 20250021230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => PHYSICALLY-DRIVEN GENERATION OF MANY-PORTED STORAGE ARRAYS [patent_app_type] => utility [patent_app_number] => 18/350145 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350145
Physically-driven generation of many-ported storage arrays Jul 10, 2023 Issued
Array ( [id] => 18696104 [patent_doc_number] => 20230326535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/333661 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333661 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333661
Semiconductor device Jun 12, 2023 Issued
Array ( [id] => 19037841 [patent_doc_number] => 20240087656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/332753 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332753
Semiconductor memory device Jun 11, 2023 Issued
Array ( [id] => 20258843 [patent_doc_number] => 12431206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Power amplifier circuit [patent_app_type] => utility [patent_app_number] => 18/327343 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4392 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327343 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327343
Power amplifier circuit May 31, 2023 Issued
Array ( [id] => 20531865 [patent_doc_number] => 12550316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/321511 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 7006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321511
Semiconductor memory device May 21, 2023 Issued
Array ( [id] => 19459935 [patent_doc_number] => 12100436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Method and system to balance ground bounce [patent_app_type] => utility [patent_app_number] => 18/321552 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321552
Method and system to balance ground bounce May 21, 2023 Issued
Array ( [id] => 19900033 [patent_doc_number] => 12277965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Memory structure and method for operating the same [patent_app_type] => utility [patent_app_number] => 18/319513 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319513
Memory structure and method for operating the same May 17, 2023 Issued
Array ( [id] => 20564846 [patent_doc_number] => 12567460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Tracking worst case memory cells by suppressing tracking wordline voltage [patent_app_type] => utility [patent_app_number] => 18/315619 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 3473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315619
Tracking worst case memory cells by suppressing tracking wordline voltage May 10, 2023 Issued
Array ( [id] => 19204604 [patent_doc_number] => 20240176503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION ACCORDING TO INCREMENTAL STEP PULSE PROGRAMMING METHOD, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/312459 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312459
Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device May 3, 2023 Issued
Array ( [id] => 19544912 [patent_doc_number] => 20240361948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => BOOSTED DRIVER CIRCUITRY OF A LOW VOLTAGE SUPPLY MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/141229 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141229
Boosted driver circuitry of a low voltage supply memory controller Apr 27, 2023 Issued
Array ( [id] => 19912364 [patent_doc_number] => 12288582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Semiconductor memory device and method for compensating slew rate using impedance calibration [patent_app_type] => utility [patent_app_number] => 18/306987 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306987
Semiconductor memory device and method for compensating slew rate using impedance calibration Apr 24, 2023 Issued
Array ( [id] => 19398716 [patent_doc_number] => 12073082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => High capacity memory circuit with low effective latency [patent_app_type] => utility [patent_app_number] => 18/306073 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 15047 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306073
High capacity memory circuit with low effective latency Apr 23, 2023 Issued
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