Search

Amelie R. Davis

Examiner (ID: 10149)

Most Active Art Unit
3793
Art Unit(s)
3798, 3793, 3737
Total Applications
502
Issued Applications
275
Pending Applications
93
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4177340 [patent_doc_number] => 06158029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method of testing an integrated circuit having a memory and a test circuit' [patent_app_type] => 1 [patent_app_number] => 9/395320 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2425 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158029.pdf [firstpage_image] =>[orig_patent_app_number] => 395320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395320
Method of testing an integrated circuit having a memory and a test circuit Sep 12, 1999 Issued
Array ( [id] => 4293151 [patent_doc_number] => 06247159 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus for encoding a binary signal' [patent_app_type] => 1 [patent_app_number] => 9/389872 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 9688 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247159.pdf [firstpage_image] =>[orig_patent_app_number] => 389872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389872
Method and apparatus for encoding a binary signal Sep 1, 1999 Issued
Array ( [id] => 1567725 [patent_doc_number] => 06363510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits' [patent_app_type] => B1 [patent_app_number] => 09/386946 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10302 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363510.pdf [firstpage_image] =>[orig_patent_app_number] => 09386946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386946
Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits Aug 30, 1999 Issued
Array ( [id] => 1567672 [patent_doc_number] => 06363504 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation' [patent_app_type] => B1 [patent_app_number] => 09/386945 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10288 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363504.pdf [firstpage_image] =>[orig_patent_app_number] => 09386945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386945
Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation Aug 30, 1999 Issued
Array ( [id] => 1525012 [patent_doc_number] => 06415404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method of an apparatus for designing test facile semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/384950 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415404.pdf [firstpage_image] =>[orig_patent_app_number] => 09384950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384950
Method of an apparatus for designing test facile semiconductor integrated circuit Aug 26, 1999 Issued
09/383471 DECODING SYSTEM FOR ERROR CORRECTION CODE Aug 25, 1999 Abandoned
Array ( [id] => 1407878 [patent_doc_number] => 06560746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Parallel CRC generation circuit for generating a CRC code' [patent_app_type] => B1 [patent_app_number] => 09/382591 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6721 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 688 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560746.pdf [firstpage_image] =>[orig_patent_app_number] => 09382591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382591
Parallel CRC generation circuit for generating a CRC code Aug 24, 1999 Issued
Array ( [id] => 1549837 [patent_doc_number] => 06374386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Device and method for inserting previously known bits in input stage of channel encoder' [patent_app_type] => B1 [patent_app_number] => 09/378371 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10345 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374386.pdf [firstpage_image] =>[orig_patent_app_number] => 09378371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378371
Device and method for inserting previously known bits in input stage of channel encoder Aug 19, 1999 Issued
Array ( [id] => 1431457 [patent_doc_number] => 06523148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Majority decision method for improved frame error rate in the digital enhanced cordless telecommunications system' [patent_app_type] => B1 [patent_app_number] => 09/377877 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523148.pdf [firstpage_image] =>[orig_patent_app_number] => 09377877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377877
Majority decision method for improved frame error rate in the digital enhanced cordless telecommunications system Aug 18, 1999 Issued
Array ( [id] => 1557426 [patent_doc_number] => 06349400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Optical disc recording/reproducing method, optical disc and optical disc device' [patent_app_type] => B1 [patent_app_number] => 09/371115 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 41 [patent_no_of_words] => 12727 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349400.pdf [firstpage_image] =>[orig_patent_app_number] => 09371115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371115
Optical disc recording/reproducing method, optical disc and optical disc device Aug 9, 1999 Issued
Array ( [id] => 1466500 [patent_doc_number] => 06393593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Tester and method for testing LSI designed for scan method' [patent_app_type] => B1 [patent_app_number] => 09/368579 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4727 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393593.pdf [firstpage_image] =>[orig_patent_app_number] => 09368579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368579
Tester and method for testing LSI designed for scan method Aug 4, 1999 Issued
Array ( [id] => 1557411 [patent_doc_number] => 06349397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Signal processing apparatus having non-volatile memory and programming method of the non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 09/365893 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5897 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349397.pdf [firstpage_image] =>[orig_patent_app_number] => 09365893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365893
Signal processing apparatus having non-volatile memory and programming method of the non-volatile memory Aug 2, 1999 Issued
Array ( [id] => 1519768 [patent_doc_number] => 06421799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Redundancy correction ROM' [patent_app_type] => B1 [patent_app_number] => 09/364704 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421799.pdf [firstpage_image] =>[orig_patent_app_number] => 09364704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364704
Redundancy correction ROM Jul 29, 1999 Issued
Array ( [id] => 1567696 [patent_doc_number] => 06438721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for testing a current mode interpolator' [patent_app_type] => B1 [patent_app_number] => 09/362543 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3113 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438721.pdf [firstpage_image] =>[orig_patent_app_number] => 09362543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362543
Method for testing a current mode interpolator Jul 27, 1999 Issued
Array ( [id] => 1481849 [patent_doc_number] => 06345374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Code error correcting apparatus' [patent_app_type] => B1 [patent_app_number] => 09/354961 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3564 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345374.pdf [firstpage_image] =>[orig_patent_app_number] => 09354961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354961
Code error correcting apparatus Jul 15, 1999 Issued
Array ( [id] => 4116899 [patent_doc_number] => 06067654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'ATM switch and control method thereof' [patent_app_type] => 1 [patent_app_number] => 9/351126 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3901 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067654.pdf [firstpage_image] =>[orig_patent_app_number] => 351126 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351126
ATM switch and control method thereof Jul 11, 1999 Issued
Array ( [id] => 7642333 [patent_doc_number] => 06430713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'System and method for constructing low complexity block coders' [patent_app_type] => B1 [patent_app_number] => 09/345579 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4234 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430713.pdf [firstpage_image] =>[orig_patent_app_number] => 09345579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345579
System and method for constructing low complexity block coders Jun 29, 1999 Issued
Array ( [id] => 4374453 [patent_doc_number] => 06202179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method and apparatus for testing cells in a memory device with compressed data and for replacing defective cells' [patent_app_type] => 1 [patent_app_number] => 9/333999 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4262 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202179.pdf [firstpage_image] =>[orig_patent_app_number] => 333999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333999
Method and apparatus for testing cells in a memory device with compressed data and for replacing defective cells Jun 14, 1999 Issued
Array ( [id] => 4118806 [patent_doc_number] => 06098191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Storage unit and storage unit subsystem' [patent_app_type] => 1 [patent_app_number] => 9/327158 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 42 [patent_no_of_words] => 12172 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098191.pdf [firstpage_image] =>[orig_patent_app_number] => 327158 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327158
Storage unit and storage unit subsystem Jun 2, 1999 Issued
Array ( [id] => 4101316 [patent_doc_number] => 06018814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Star-I: scalable tester architecture with I-cached SIMD technology' [patent_app_type] => 1 [patent_app_number] => 9/322689 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6128 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018814.pdf [firstpage_image] =>[orig_patent_app_number] => 322689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322689
Star-I: scalable tester architecture with I-cached SIMD technology May 31, 1999 Issued
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