Search

Amelie R. Davis

Examiner (ID: 10149)

Most Active Art Unit
3793
Art Unit(s)
3798, 3793, 3737
Total Applications
502
Issued Applications
275
Pending Applications
93
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1432429 [patent_doc_number] => 06505321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Fault tolerant parity generation' [patent_app_type] => B1 [patent_app_number] => 09/315437 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505321.pdf [firstpage_image] =>[orig_patent_app_number] => 09315437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315437
Fault tolerant parity generation May 19, 1999 Issued
Array ( [id] => 1444025 [patent_doc_number] => 06336200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method for validating communicated packets of data and for locating erroneous packets' [patent_app_type] => B1 [patent_app_number] => 09/314120 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4009 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336200.pdf [firstpage_image] =>[orig_patent_app_number] => 09314120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314120
Method for validating communicated packets of data and for locating erroneous packets May 18, 1999 Issued
Array ( [id] => 4392660 [patent_doc_number] => 06289484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Disk drive employing off-line scan to collect selection-control data for subsequently deciding whether to verify after write' [patent_app_type] => 1 [patent_app_number] => 9/314871 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9076 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289484.pdf [firstpage_image] =>[orig_patent_app_number] => 314871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314871
Disk drive employing off-line scan to collect selection-control data for subsequently deciding whether to verify after write May 18, 1999 Issued
Array ( [id] => 1567713 [patent_doc_number] => 06438726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of dual use of non-volatile memory for error correction' [patent_app_type] => B1 [patent_app_number] => 09/314575 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8072 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438726.pdf [firstpage_image] =>[orig_patent_app_number] => 09314575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314575
Method of dual use of non-volatile memory for error correction May 17, 1999 Issued
Array ( [id] => 1592551 [patent_doc_number] => 06360347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Error correction method for a memory device' [patent_app_type] => B1 [patent_app_number] => 09/314576 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6680 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360347.pdf [firstpage_image] =>[orig_patent_app_number] => 09314576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314576
Error correction method for a memory device May 17, 1999 Issued
Array ( [id] => 1424097 [patent_doc_number] => 06539514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Read while write method in data storage device' [patent_app_type] => B1 [patent_app_number] => 09/310407 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539514.pdf [firstpage_image] =>[orig_patent_app_number] => 09310407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310407
Read while write method in data storage device May 11, 1999 Issued
Array ( [id] => 4325186 [patent_doc_number] => 06327685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Logic built-in self test' [patent_app_type] => 1 [patent_app_number] => 9/310444 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2833 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327685.pdf [firstpage_image] =>[orig_patent_app_number] => 310444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310444
Logic built-in self test May 11, 1999 Issued
Array ( [id] => 1540695 [patent_doc_number] => 06490700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Memory device testing apparatus and data selection circuit' [patent_app_type] => B1 [patent_app_number] => 09/310173 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9051 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490700.pdf [firstpage_image] =>[orig_patent_app_number] => 09310173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310173
Memory device testing apparatus and data selection circuit May 11, 1999 Issued
Array ( [id] => 7634953 [patent_doc_number] => 06381713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method for responding to transmission errors in a digital communication system according to characteristics of flawed information fields' [patent_app_type] => B1 [patent_app_number] => 09/309352 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6586 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381713.pdf [firstpage_image] =>[orig_patent_app_number] => 09309352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309352
Method for responding to transmission errors in a digital communication system according to characteristics of flawed information fields May 10, 1999 Issued
09/117157 FINITE FIELD MULTIPLIER CIRCUIT AND USE THEREOF IN AN ERROR CORRECTOR DECODER May 9, 1999 Abandoned
Array ( [id] => 4293071 [patent_doc_number] => 06247153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus for testing semiconductor memory device having a plurality of memory banks' [patent_app_type] => 1 [patent_app_number] => 9/295179 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5138 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247153.pdf [firstpage_image] =>[orig_patent_app_number] => 295179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295179
Method and apparatus for testing semiconductor memory device having a plurality of memory banks Apr 19, 1999 Issued
Array ( [id] => 1540670 [patent_doc_number] => 06490694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Electronic test system for microprocessor based boards' [patent_app_type] => B1 [patent_app_number] => 09/295224 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4135 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490694.pdf [firstpage_image] =>[orig_patent_app_number] => 09295224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295224
Electronic test system for microprocessor based boards Apr 18, 1999 Issued
Array ( [id] => 7638560 [patent_doc_number] => 06397361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Reduced-pin integrated circuit I/O test' [patent_app_type] => B1 [patent_app_number] => 09/285911 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8238 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397361.pdf [firstpage_image] =>[orig_patent_app_number] => 09285911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285911
Reduced-pin integrated circuit I/O test Apr 1, 1999 Issued
Array ( [id] => 1602142 [patent_doc_number] => 06385749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method and arrangement for controlling multiple test access port control modules' [patent_app_type] => B1 [patent_app_number] => 09/283809 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5182 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385749.pdf [firstpage_image] =>[orig_patent_app_number] => 09283809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283809
Method and arrangement for controlling multiple test access port control modules Mar 31, 1999 Issued
Array ( [id] => 1572587 [patent_doc_number] => 06378094 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method and system for testing cluster circuits in a boundary scan environment' [patent_app_type] => B1 [patent_app_number] => 09/283421 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3281 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378094.pdf [firstpage_image] =>[orig_patent_app_number] => 09283421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283421
Method and system for testing cluster circuits in a boundary scan environment Mar 31, 1999 Issued
Array ( [id] => 4351184 [patent_doc_number] => 06334198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method and arrangement for controlling multiply-activated test access port control modules' [patent_app_type] => 1 [patent_app_number] => 9/283171 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334198.pdf [firstpage_image] =>[orig_patent_app_number] => 283171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283171
Method and arrangement for controlling multiply-activated test access port control modules Mar 31, 1999 Issued
Array ( [id] => 4423771 [patent_doc_number] => 06311302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method and arrangement for hierarchical control of multiple test access port control modules' [patent_app_type] => 1 [patent_app_number] => 9/283648 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311302.pdf [firstpage_image] =>[orig_patent_app_number] => 283648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283648
Method and arrangement for hierarchical control of multiple test access port control modules Mar 31, 1999 Issued
Array ( [id] => 1602331 [patent_doc_number] => 06493841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and apparatus for determining expected values during circuit design verification' [patent_app_type] => B1 [patent_app_number] => 09/283774 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7630 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493841.pdf [firstpage_image] =>[orig_patent_app_number] => 09283774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283774
Method and apparatus for determining expected values during circuit design verification Mar 30, 1999 Issued
Array ( [id] => 4299572 [patent_doc_number] => 06282677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Interleaving apparatus' [patent_app_type] => 1 [patent_app_number] => 9/280544 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3811 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282677.pdf [firstpage_image] =>[orig_patent_app_number] => 280544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280544
Interleaving apparatus Mar 29, 1999 Issued
Array ( [id] => 4295361 [patent_doc_number] => 06324670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Checksum generator with minimum overflow' [patent_app_type] => 1 [patent_app_number] => 9/275201 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324670.pdf [firstpage_image] =>[orig_patent_app_number] => 275201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275201
Checksum generator with minimum overflow Mar 23, 1999 Issued
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