Search

Amelie R. Davis

Examiner (ID: 10149)

Most Active Art Unit
3793
Art Unit(s)
3798, 3793, 3737
Total Applications
502
Issued Applications
275
Pending Applications
93
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4299600 [patent_doc_number] => 06282679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Pattern and method of metal line package level test for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/188235 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2763 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282679.pdf [firstpage_image] =>[orig_patent_app_number] => 188235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188235
Pattern and method of metal line package level test for semiconductor device Nov 8, 1998 Issued
Array ( [id] => 4176308 [patent_doc_number] => 06105047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method and apparatus for trading performance for precision when processing denormal numbers in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/188868 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4243 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105047.pdf [firstpage_image] =>[orig_patent_app_number] => 188868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188868
Method and apparatus for trading performance for precision when processing denormal numbers in a computer system Nov 8, 1998 Issued
Array ( [id] => 4427349 [patent_doc_number] => 06226772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Pipelined combined system for producing error correction code symbols and error syndromes for large ECC redundancy' [patent_app_type] => 1 [patent_app_number] => 9/187144 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4091 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226772.pdf [firstpage_image] =>[orig_patent_app_number] => 187144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187144
Pipelined combined system for producing error correction code symbols and error syndromes for large ECC redundancy Nov 5, 1998 Issued
Array ( [id] => 1466509 [patent_doc_number] => 06393596 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Missing pulse detector using synchronous detection' [patent_app_type] => B1 [patent_app_number] => 09/183832 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1452 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393596.pdf [firstpage_image] =>[orig_patent_app_number] => 09183832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183832
Missing pulse detector using synchronous detection Oct 29, 1998 Issued
Array ( [id] => 4177526 [patent_doc_number] => 06158040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Rotated data-aligmnent in wade embedded DRAM for page-mode column ECC in a DVD controller' [patent_app_type] => 1 [patent_app_number] => 9/182345 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158040.pdf [firstpage_image] =>[orig_patent_app_number] => 182345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182345
Rotated data-aligmnent in wade embedded DRAM for page-mode column ECC in a DVD controller Oct 28, 1998 Issued
Array ( [id] => 4423079 [patent_doc_number] => 06272658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and system for reliable broadcasting of data files and streams' [patent_app_type] => 1 [patent_app_number] => 9/179083 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6331 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272658.pdf [firstpage_image] =>[orig_patent_app_number] => 179083 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179083
Method and system for reliable broadcasting of data files and streams Oct 26, 1998 Issued
Array ( [id] => 4422702 [patent_doc_number] => 06233707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate\'s clock' [patent_app_type] => 1 [patent_app_number] => 9/179626 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 13293 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233707.pdf [firstpage_image] =>[orig_patent_app_number] => 179626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179626
Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock Oct 26, 1998 Issued
Array ( [id] => 4239900 [patent_doc_number] => 06088827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => '1000BASE-T packetized trellis coder' [patent_app_type] => 1 [patent_app_number] => 9/178212 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5264 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088827.pdf [firstpage_image] =>[orig_patent_app_number] => 178212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178212
1000BASE-T packetized trellis coder Oct 22, 1998 Issued
Array ( [id] => 4172121 [patent_doc_number] => 06125470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Distributive encoder for encoding error signals which represent signal peak errors in data signals for correcting erroneous signal baseline conditions' [patent_app_type] => 1 [patent_app_number] => 9/176633 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5190 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125470.pdf [firstpage_image] =>[orig_patent_app_number] => 176633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176633
Distributive encoder for encoding error signals which represent signal peak errors in data signals for correcting erroneous signal baseline conditions Oct 21, 1998 Issued
Array ( [id] => 4318661 [patent_doc_number] => 06185717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Data reception unit' [patent_app_type] => 1 [patent_app_number] => 9/173548 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3584 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185717.pdf [firstpage_image] =>[orig_patent_app_number] => 173548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/173548
Data reception unit Oct 15, 1998 Issued
Array ( [id] => 4148339 [patent_doc_number] => 06128760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method and apparatus for calculating a CRC remainder' [patent_app_type] => 1 [patent_app_number] => 9/170497 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4333 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128760.pdf [firstpage_image] =>[orig_patent_app_number] => 170497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170497
Method and apparatus for calculating a CRC remainder Oct 12, 1998 Issued
Array ( [id] => 4374595 [patent_doc_number] => 06202185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Methods and apparatus for facilitating scan testing of circuitry' [patent_app_type] => 1 [patent_app_number] => 9/169177 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 7564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202185.pdf [firstpage_image] =>[orig_patent_app_number] => 169177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169177
Methods and apparatus for facilitating scan testing of circuitry Oct 7, 1998 Issued
Array ( [id] => 4333848 [patent_doc_number] => 06317855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method and apparatus for checking data error correction' [patent_app_type] => 1 [patent_app_number] => 9/162142 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8670 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317855.pdf [firstpage_image] =>[orig_patent_app_number] => 162142 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162142
Method and apparatus for checking data error correction Sep 28, 1998 Issued
Array ( [id] => 3999918 [patent_doc_number] => 05960011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Viterbi decoder' [patent_app_type] => 1 [patent_app_number] => 9/159636 [patent_app_country] => US [patent_app_date] => 1998-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7693 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960011.pdf [firstpage_image] =>[orig_patent_app_number] => 159636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159636
Viterbi decoder Sep 23, 1998 Issued
Array ( [id] => 5803600 [patent_doc_number] => 20020010885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'CONFIGURABLE INTEGRATED CIRCUIT AND METHOD OF TESTING THE SAME' [patent_app_type] => new [patent_app_number] => 09/154027 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5217 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010885.pdf [firstpage_image] =>[orig_patent_app_number] => 09154027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154027
Configurable integrated circuit and method of testing the same Sep 15, 1998 Issued
09/154381 LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS Sep 15, 1998 Abandoned
Array ( [id] => 4427341 [patent_doc_number] => 06226764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Integrated circuit memory devices including internal stress voltage generating circuits and methods for built-in self test (BIST)' [patent_app_type] => 1 [patent_app_number] => 9/154060 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3045 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226764.pdf [firstpage_image] =>[orig_patent_app_number] => 154060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154060
Integrated circuit memory devices including internal stress voltage generating circuits and methods for built-in self test (BIST) Sep 15, 1998 Issued
Array ( [id] => 1553181 [patent_doc_number] => 06446230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests' [patent_app_type] => B1 [patent_app_number] => 09/152940 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 6736 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446230.pdf [firstpage_image] =>[orig_patent_app_number] => 09152940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/152940
Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests Sep 13, 1998 Issued
Array ( [id] => 1444034 [patent_doc_number] => 06336202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Data storage system, storage medium and method of controlling a data storage system' [patent_app_type] => B1 [patent_app_number] => 09/149535 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5375 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336202.pdf [firstpage_image] =>[orig_patent_app_number] => 09149535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149535
Data storage system, storage medium and method of controlling a data storage system Sep 7, 1998 Issued
09/146982 CYCLIC TRELLIS CODED MODULATION Sep 2, 1998 Abandoned
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