Search

Amelie R. Davis

Examiner (ID: 10149)

Most Active Art Unit
3793
Art Unit(s)
3798, 3793, 3737
Total Applications
502
Issued Applications
275
Pending Applications
93
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4274308 [patent_doc_number] => 06209117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method for canceling abnormal synchronization signal' [patent_app_type] => 1 [patent_app_number] => 9/145302 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2929 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209117.pdf [firstpage_image] =>[orig_patent_app_number] => 145302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145302
Method for canceling abnormal synchronization signal Sep 1, 1998 Issued
Array ( [id] => 4179829 [patent_doc_number] => 06115834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for quickly identifying floating cells by a bit-line coupling pattern (BLCP)' [patent_app_type] => 1 [patent_app_number] => 9/146042 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2580 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115834.pdf [firstpage_image] =>[orig_patent_app_number] => 146042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146042
Method for quickly identifying floating cells by a bit-line coupling pattern (BLCP) Sep 1, 1998 Issued
Array ( [id] => 4281662 [patent_doc_number] => 06260170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for controlling memory and digital recording/reproducing device using the same' [patent_app_type] => 1 [patent_app_number] => 9/141606 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7017 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260170.pdf [firstpage_image] =>[orig_patent_app_number] => 141606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141606
Method for controlling memory and digital recording/reproducing device using the same Aug 27, 1998 Issued
Array ( [id] => 4424997 [patent_doc_number] => 06230291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Microcomputer including burn-in test circuit and burn-in test method thereof including mode switching device' [patent_app_type] => 1 [patent_app_number] => 9/143241 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6405 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230291.pdf [firstpage_image] =>[orig_patent_app_number] => 143241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143241
Microcomputer including burn-in test circuit and burn-in test method thereof including mode switching device Aug 27, 1998 Issued
Array ( [id] => 4177352 [patent_doc_number] => 06158030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'System and method for aligning output signals in massively parallel testers and other electronic devices' [patent_app_type] => 1 [patent_app_number] => 9/137738 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2650 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158030.pdf [firstpage_image] =>[orig_patent_app_number] => 137738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137738
System and method for aligning output signals in massively parallel testers and other electronic devices Aug 20, 1998 Issued
Array ( [id] => 4148438 [patent_doc_number] => 06128765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Maximum A posterior estimator with fast sigma calculator' [patent_app_type] => 1 [patent_app_number] => 9/137260 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4299 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128765.pdf [firstpage_image] =>[orig_patent_app_number] => 137260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137260
Maximum A posterior estimator with fast sigma calculator Aug 19, 1998 Issued
Array ( [id] => 4311002 [patent_doc_number] => 06212660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Methods and apparatuses for identification of the position of data packets which are located in a serial received data stream' [patent_app_type] => 1 [patent_app_number] => 9/136571 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5801 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212660.pdf [firstpage_image] =>[orig_patent_app_number] => 136571 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136571
Methods and apparatuses for identification of the position of data packets which are located in a serial received data stream Aug 18, 1998 Issued
Array ( [id] => 4392559 [patent_doc_number] => 06289477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Fast-scan-flop and integrated circuit device incorporating the same' [patent_app_type] => 1 [patent_app_number] => 9/136071 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6462 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289477.pdf [firstpage_image] =>[orig_patent_app_number] => 136071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136071
Fast-scan-flop and integrated circuit device incorporating the same Aug 17, 1998 Issued
Array ( [id] => 4366878 [patent_doc_number] => 06286123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Circuit for calculating error position polynomial at high speed' [patent_app_type] => 1 [patent_app_number] => 9/132674 [patent_app_country] => US [patent_app_date] => 1998-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2939 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 529 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286123.pdf [firstpage_image] =>[orig_patent_app_number] => 132674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132674
Circuit for calculating error position polynomial at high speed Aug 11, 1998 Issued
Array ( [id] => 4118792 [patent_doc_number] => 06098190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method and apparatus for use of a host address to validate accessed data' [patent_app_type] => 1 [patent_app_number] => 9/129031 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2400 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098190.pdf [firstpage_image] =>[orig_patent_app_number] => 129031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129031
Method and apparatus for use of a host address to validate accessed data Aug 3, 1998 Issued
Array ( [id] => 4148395 [patent_doc_number] => 06128762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Updating and reading data and parity blocks in a shared disk system with request forwarding' [patent_app_type] => 1 [patent_app_number] => 9/128754 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6870 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128762.pdf [firstpage_image] =>[orig_patent_app_number] => 128754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128754
Updating and reading data and parity blocks in a shared disk system with request forwarding Aug 3, 1998 Issued
Array ( [id] => 4177326 [patent_doc_number] => 06158028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/128781 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158028.pdf [firstpage_image] =>[orig_patent_app_number] => 128781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128781
Semiconductor integrated circuit Aug 3, 1998 Issued
Array ( [id] => 4374664 [patent_doc_number] => 06202190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Process for determining the start- up time of a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/127598 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5868 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202190.pdf [firstpage_image] =>[orig_patent_app_number] => 127598 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127598
Process for determining the start- up time of a data processing system Jul 30, 1998 Issued
Array ( [id] => 4374622 [patent_doc_number] => 06202187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Pattern generator for use in a semiconductor test device' [patent_app_type] => 1 [patent_app_number] => 9/127537 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3274 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202187.pdf [firstpage_image] =>[orig_patent_app_number] => 127537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127537
Pattern generator for use in a semiconductor test device Jul 30, 1998 Issued
Array ( [id] => 4412855 [patent_doc_number] => 06298463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Parallel concatenated convolutional coding' [patent_app_type] => 1 [patent_app_number] => 9/126993 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298463.pdf [firstpage_image] =>[orig_patent_app_number] => 126993 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/126993
Parallel concatenated convolutional coding Jul 30, 1998 Issued
Array ( [id] => 4375147 [patent_doc_number] => 06170071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method for optimizing test fixtures to minimize vector load time for automated test equipment' [patent_app_type] => 1 [patent_app_number] => 9/123380 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3062 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170071.pdf [firstpage_image] =>[orig_patent_app_number] => 123380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123380
Method for optimizing test fixtures to minimize vector load time for automated test equipment Jul 26, 1998 Issued
Array ( [id] => 4380290 [patent_doc_number] => 06192495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'On-board testing circuit and method for improving testing of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/113940 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192495.pdf [firstpage_image] =>[orig_patent_app_number] => 113940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113940
On-board testing circuit and method for improving testing of integrated circuits Jul 9, 1998 Issued
Array ( [id] => 4324560 [patent_doc_number] => 06189119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Semiconductor memory device having test mode' [patent_app_type] => 1 [patent_app_number] => 9/111881 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4169 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189119.pdf [firstpage_image] =>[orig_patent_app_number] => 111881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111881
Semiconductor memory device having test mode Jul 7, 1998 Issued
Array ( [id] => 4149252 [patent_doc_number] => 06016568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'High rate trellis coding and decoding method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/110700 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 8143 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016568.pdf [firstpage_image] =>[orig_patent_app_number] => 110700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110700
High rate trellis coding and decoding method and apparatus Jul 6, 1998 Issued
Array ( [id] => 4366708 [patent_doc_number] => 06286115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'On-chip testing circuit and method for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/106813 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3194 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286115.pdf [firstpage_image] =>[orig_patent_app_number] => 106813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106813
On-chip testing circuit and method for integrated circuits Jun 28, 1998 Issued
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