Search

Amelie R. Davis

Examiner (ID: 10149)

Most Active Art Unit
3793
Art Unit(s)
3798, 3793, 3737
Total Applications
502
Issued Applications
275
Pending Applications
93
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4177298 [patent_doc_number] => 06158026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Scrambling apparatus, method thereof, descrambling apparatus, and method thereof' [patent_app_type] => 1 [patent_app_number] => 9/102737 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 10588 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158026.pdf [firstpage_image] =>[orig_patent_app_number] => 102737 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102737
Scrambling apparatus, method thereof, descrambling apparatus, and method thereof Jun 21, 1998 Issued
Array ( [id] => 4366753 [patent_doc_number] => 06286117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Circuits and methods for testing logic devices by modulating a test voltage with a noise signal' [patent_app_type] => 1 [patent_app_number] => 9/102202 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2641 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286117.pdf [firstpage_image] =>[orig_patent_app_number] => 102202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102202
Circuits and methods for testing logic devices by modulating a test voltage with a noise signal Jun 21, 1998 Issued
Array ( [id] => 4258414 [patent_doc_number] => 06145110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Digital data decoder that derives codeword estimates from soft data' [patent_app_type] => 1 [patent_app_number] => 9/102291 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4448 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145110.pdf [firstpage_image] =>[orig_patent_app_number] => 102291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102291
Digital data decoder that derives codeword estimates from soft data Jun 21, 1998 Issued
Array ( [id] => 4085982 [patent_doc_number] => 06009548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Error correcting code retrofit method and apparatus for multiple memory configurations' [patent_app_type] => 1 [patent_app_number] => 9/023969 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14020 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009548.pdf [firstpage_image] =>[orig_patent_app_number] => 023969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023969
Error correcting code retrofit method and apparatus for multiple memory configurations Jun 17, 1998 Issued
Array ( [id] => 4335921 [patent_doc_number] => 06243839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns' [patent_app_type] => 1 [patent_app_number] => 9/094752 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243839.pdf [firstpage_image] =>[orig_patent_app_number] => 094752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094752
Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns Jun 14, 1998 Issued
Array ( [id] => 4381983 [patent_doc_number] => 06256754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Memory system having internal state monitoring circuit' [patent_app_type] => 1 [patent_app_number] => 9/097470 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5028 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256754.pdf [firstpage_image] =>[orig_patent_app_number] => 097470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097470
Memory system having internal state monitoring circuit Jun 14, 1998 Issued
Array ( [id] => 4423049 [patent_doc_number] => 06272655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of reducing test time for NVM cell-based FPGA' [patent_app_type] => 1 [patent_app_number] => 9/096142 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4252 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272655.pdf [firstpage_image] =>[orig_patent_app_number] => 096142 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096142
Method of reducing test time for NVM cell-based FPGA Jun 10, 1998 Issued
Array ( [id] => 4380275 [patent_doc_number] => 06192494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Apparatus and method for analyzing circuit test results and recording medium storing analytical program therefor' [patent_app_type] => 1 [patent_app_number] => 9/095711 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5379 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192494.pdf [firstpage_image] =>[orig_patent_app_number] => 095711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095711
Apparatus and method for analyzing circuit test results and recording medium storing analytical program therefor Jun 10, 1998 Issued
Array ( [id] => 4392544 [patent_doc_number] => 06289476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method and apparatus for testing the timing of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/095673 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4174 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289476.pdf [firstpage_image] =>[orig_patent_app_number] => 095673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095673
Method and apparatus for testing the timing of integrated circuits Jun 9, 1998 Issued
Array ( [id] => 4116820 [patent_doc_number] => 06067649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method and apparatus for a low power self test of a memory subsystem' [patent_app_type] => 1 [patent_app_number] => 9/095435 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067649.pdf [firstpage_image] =>[orig_patent_app_number] => 095435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095435
Method and apparatus for a low power self test of a memory subsystem Jun 9, 1998 Issued
Array ( [id] => 4335962 [patent_doc_number] => 06243842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method and apparatus for operating on a memory unit via a JTAG port' [patent_app_type] => 1 [patent_app_number] => 9/093943 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3589 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243842.pdf [firstpage_image] =>[orig_patent_app_number] => 093943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093943
Method and apparatus for operating on a memory unit via a JTAG port Jun 7, 1998 Issued
Array ( [id] => 4271167 [patent_doc_number] => 06223318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'IC tester having region in which various test conditions are stored' [patent_app_type] => 1 [patent_app_number] => 9/092900 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3466 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223318.pdf [firstpage_image] =>[orig_patent_app_number] => 092900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092900
IC tester having region in which various test conditions are stored Jun 7, 1998 Issued
Array ( [id] => 4209781 [patent_doc_number] => 06154870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Signal error-correction system and method' [patent_app_type] => 1 [patent_app_number] => 9/089874 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7858 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154870.pdf [firstpage_image] =>[orig_patent_app_number] => 089874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089874
Signal error-correction system and method Jun 3, 1998 Issued
Array ( [id] => 4317000 [patent_doc_number] => 06199183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method of forming a scan path network' [patent_app_type] => 1 [patent_app_number] => 9/090170 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4531 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199183.pdf [firstpage_image] =>[orig_patent_app_number] => 090170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090170
Method of forming a scan path network Jun 3, 1998 Issued
Array ( [id] => 3968271 [patent_doc_number] => 05983386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'ATM switch and control method thereof' [patent_app_type] => 1 [patent_app_number] => 9/087899 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3901 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983386.pdf [firstpage_image] =>[orig_patent_app_number] => 087899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087899
ATM switch and control method thereof May 31, 1998 Issued
Array ( [id] => 4371734 [patent_doc_number] => 06216247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => '32-bit mode for a 64-bit ECC capable memory subsystem' [patent_app_type] => 1 [patent_app_number] => 9/087390 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4542 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216247.pdf [firstpage_image] =>[orig_patent_app_number] => 087390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087390
32-bit mode for a 64-bit ECC capable memory subsystem May 28, 1998 Issued
Array ( [id] => 4209700 [patent_doc_number] => 06154866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Reproducing apparatus, error correcting unit and error correcting method' [patent_app_type] => 1 [patent_app_number] => 9/095701 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6147 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154866.pdf [firstpage_image] =>[orig_patent_app_number] => 095701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095701
Reproducing apparatus, error correcting unit and error correcting method May 28, 1998 Issued
Array ( [id] => 4335949 [patent_doc_number] => 06243841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Automated test and evaluation sampling system and method' [patent_app_type] => 1 [patent_app_number] => 9/087434 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4486 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243841.pdf [firstpage_image] =>[orig_patent_app_number] => 087434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087434
Automated test and evaluation sampling system and method May 28, 1998 Issued
Array ( [id] => 4101651 [patent_doc_number] => 06163871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'RAM based error correction code encoder and syndrome generator with programmable interleaving degrees' [patent_app_type] => 1 [patent_app_number] => 9/087433 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7942 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163871.pdf [firstpage_image] =>[orig_patent_app_number] => 087433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087433
RAM based error correction code encoder and syndrome generator with programmable interleaving degrees May 28, 1998 Issued
Array ( [id] => 4111018 [patent_doc_number] => 06134696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Encoding and decoding rate-1/n convolutional codes and their punctured versions' [patent_app_type] => 1 [patent_app_number] => 9/087459 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4308 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134696.pdf [firstpage_image] =>[orig_patent_app_number] => 087459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087459
Encoding and decoding rate-1/n convolutional codes and their punctured versions May 27, 1998 Issued
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