Search

Amelie R. Davis

Examiner (ID: 10149)

Most Active Art Unit
3793
Art Unit(s)
3798, 3793, 3737
Total Applications
502
Issued Applications
275
Pending Applications
93
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4224725 [patent_doc_number] => 06079043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Magnetic disk apparatus' [patent_app_type] => 1 [patent_app_number] => 9/086023 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6361 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079043.pdf [firstpage_image] =>[orig_patent_app_number] => 086023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086023
Magnetic disk apparatus May 27, 1998 Issued
Array ( [id] => 4427015 [patent_doc_number] => 06195785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Process and device for validating/invalidating a message sent over an information transmission network by means of a response in a communication frame' [patent_app_type] => 1 [patent_app_number] => 9/084088 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1761 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195785.pdf [firstpage_image] =>[orig_patent_app_number] => 084088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084088
Process and device for validating/invalidating a message sent over an information transmission network by means of a response in a communication frame May 25, 1998 Issued
Array ( [id] => 4255753 [patent_doc_number] => 06119250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/083389 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13546 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119250.pdf [firstpage_image] =>[orig_patent_app_number] => 083389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083389
Semiconductor integrated circuit May 21, 1998 Issued
Array ( [id] => 4374693 [patent_doc_number] => 06175938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Scheme for the reduction of extra standby current induced by process defects' [patent_app_type] => 1 [patent_app_number] => 9/081663 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1572 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175938.pdf [firstpage_image] =>[orig_patent_app_number] => 081663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081663
Scheme for the reduction of extra standby current induced by process defects May 19, 1998 Issued
Array ( [id] => 4423098 [patent_doc_number] => 06272659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Error correction code processor employing adjustable correction power for miscorrection minimization' [patent_app_type] => 1 [patent_app_number] => 9/080508 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9139 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272659.pdf [firstpage_image] =>[orig_patent_app_number] => 080508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080508
Error correction code processor employing adjustable correction power for miscorrection minimization May 17, 1998 Issued
Array ( [id] => 4122610 [patent_doc_number] => 06052799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'System and method for recovering a directory for a log structured array' [patent_app_type] => 1 [patent_app_number] => 9/079913 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6576 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052799.pdf [firstpage_image] =>[orig_patent_app_number] => 079913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/079913
System and method for recovering a directory for a log structured array May 14, 1998 Issued
Array ( [id] => 4293128 [patent_doc_number] => 06247157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method of encoding data signals for storage' [patent_app_type] => 1 [patent_app_number] => 9/078389 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5426 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247157.pdf [firstpage_image] =>[orig_patent_app_number] => 078389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/078389
Method of encoding data signals for storage May 12, 1998 Issued
Array ( [id] => 4177398 [patent_doc_number] => 06158033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Multiple input signature testing & diagnosis for embedded blocks in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/075350 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2867 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158033.pdf [firstpage_image] =>[orig_patent_app_number] => 075350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075350
Multiple input signature testing & diagnosis for embedded blocks in integrated circuits May 7, 1998 Issued
Array ( [id] => 4269864 [patent_doc_number] => 06138261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Concatenated coding system for satellite communications' [patent_app_type] => 1 [patent_app_number] => 9/069681 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4886 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138261.pdf [firstpage_image] =>[orig_patent_app_number] => 069681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069681
Concatenated coding system for satellite communications Apr 28, 1998 Issued
Array ( [id] => 4037372 [patent_doc_number] => 05968196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Configuration control in a programmable logic device using non-volatile elements' [patent_app_type] => 1 [patent_app_number] => 9/063872 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3188 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968196.pdf [firstpage_image] =>[orig_patent_app_number] => 063872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063872
Configuration control in a programmable logic device using non-volatile elements Apr 20, 1998 Issued
Array ( [id] => 4172079 [patent_doc_number] => 06125467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method and apparatus for partial word read through ECC block' [patent_app_type] => 1 [patent_app_number] => 9/063962 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5829 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125467.pdf [firstpage_image] =>[orig_patent_app_number] => 063962 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063962
Method and apparatus for partial word read through ECC block Apr 20, 1998 Issued
Array ( [id] => 4177446 [patent_doc_number] => 06158036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Merged memory and logic (MML) integrated circuits including built-in test circuits and methods' [patent_app_type] => 1 [patent_app_number] => 9/059754 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4884 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/158/06158036.pdf [firstpage_image] =>[orig_patent_app_number] => 059754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059754
Merged memory and logic (MML) integrated circuits including built-in test circuits and methods Apr 13, 1998 Issued
Array ( [id] => 4178535 [patent_doc_number] => 06108806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method of testing and diagnosing field programmable gate arrays' [patent_app_type] => 1 [patent_app_number] => 9/059552 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6916 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108806.pdf [firstpage_image] =>[orig_patent_app_number] => 059552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059552
Method of testing and diagnosing field programmable gate arrays Apr 12, 1998 Issued
Array ( [id] => 4167928 [patent_doc_number] => 06065145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Method for testing path delay faults in sequential logic circuits' [patent_app_type] => 1 [patent_app_number] => 9/058839 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7713 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065145.pdf [firstpage_image] =>[orig_patent_app_number] => 058839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058839
Method for testing path delay faults in sequential logic circuits Apr 12, 1998 Issued
Array ( [id] => 4037479 [patent_doc_number] => 05968200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Implied interleaving a family of systematic interleavers and deinterleavers' [patent_app_type] => 1 [patent_app_number] => 9/058346 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5677 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968200.pdf [firstpage_image] =>[orig_patent_app_number] => 058346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058346
Implied interleaving a family of systematic interleavers and deinterleavers Apr 9, 1998 Issued
Array ( [id] => 4193311 [patent_doc_number] => 06141783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Error propagation limiting encoder/decoder for multilevel decision feedback equalization' [patent_app_type] => 1 [patent_app_number] => 9/058509 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2804 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141783.pdf [firstpage_image] =>[orig_patent_app_number] => 058509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058509
Error propagation limiting encoder/decoder for multilevel decision feedback equalization Apr 9, 1998 Issued
Array ( [id] => 4224766 [patent_doc_number] => 06079046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Dynamic data transfer bandwidth control' [patent_app_type] => 1 [patent_app_number] => 9/057998 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3464 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079046.pdf [firstpage_image] =>[orig_patent_app_number] => 057998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057998
Dynamic data transfer bandwidth control Apr 8, 1998 Issued
Array ( [id] => 4204527 [patent_doc_number] => 06151692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Integrated circuit having memory built-in self test (BIST) for different memory sizes and method of operation' [patent_app_type] => 1 [patent_app_number] => 9/059620 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2739 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151692.pdf [firstpage_image] =>[orig_patent_app_number] => 059620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059620
Integrated circuit having memory built-in self test (BIST) for different memory sizes and method of operation Apr 7, 1998 Issued
Array ( [id] => 4139562 [patent_doc_number] => 06073264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Debug vector launch tool' [patent_app_type] => 1 [patent_app_number] => 9/053936 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 4 [patent_no_of_words] => 3945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073264.pdf [firstpage_image] =>[orig_patent_app_number] => 053936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053936
Debug vector launch tool Apr 1, 1998 Issued
Array ( [id] => 4257637 [patent_doc_number] => 06081915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method and apparatus for reducing the time required to test an integrated circuit using slew rate control' [patent_app_type] => 1 [patent_app_number] => 9/050157 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4138 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081915.pdf [firstpage_image] =>[orig_patent_app_number] => 050157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050157
Method and apparatus for reducing the time required to test an integrated circuit using slew rate control Mar 29, 1998 Issued
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