
Amelie R. Davis
Examiner (ID: 10149)
| Most Active Art Unit | 3793 |
| Art Unit(s) | 3798, 3793, 3737 |
| Total Applications | 502 |
| Issued Applications | 275 |
| Pending Applications | 93 |
| Abandoned Applications | 166 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4199861
[patent_doc_number] => 06038696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Digital transmission system and method comprising a product code combined with a multidimensional modulation'
[patent_app_type] => 1
[patent_app_number] => 8/987695
[patent_app_country] => US
[patent_app_date] => 1997-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 14695
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/038/06038696.pdf
[firstpage_image] =>[orig_patent_app_number] => 987695
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987695 | Digital transmission system and method comprising a product code combined with a multidimensional modulation | Dec 8, 1997 | Issued |
Array
(
[id] => 4271097
[patent_doc_number] => 06223313
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Method and apparatus for controlling and observing data in a logic block-based asic'
[patent_app_type] => 1
[patent_app_number] => 8/985790
[patent_app_country] => US
[patent_app_date] => 1997-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 24
[patent_no_of_words] => 14206
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/223/06223313.pdf
[firstpage_image] =>[orig_patent_app_number] => 985790
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/985790 | Method and apparatus for controlling and observing data in a logic block-based asic | Dec 4, 1997 | Issued |
Array
(
[id] => 4101358
[patent_doc_number] => 06018817
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Error correcting code retrofit method and apparatus for multiple memory configurations'
[patent_app_type] => 1
[patent_app_number] => 8/984240
[patent_app_country] => US
[patent_app_date] => 1997-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 13869
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018817.pdf
[firstpage_image] =>[orig_patent_app_number] => 984240
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/984240 | Error correcting code retrofit method and apparatus for multiple memory configurations | Dec 2, 1997 | Issued |
Array
(
[id] => 4101531
[patent_doc_number] => 06163862
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'On-chip test circuit for evaluating an on-chip signal using an external test signal'
[patent_app_type] => 1
[patent_app_number] => 8/980524
[patent_app_country] => US
[patent_app_date] => 1997-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 5608
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163862.pdf
[firstpage_image] =>[orig_patent_app_number] => 980524
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980524 | On-chip test circuit for evaluating an on-chip signal using an external test signal | Nov 30, 1997 | Issued |
Array
(
[id] => 4115256
[patent_doc_number] => 06049902
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Method and system in a data communications system for the establishment of multiple, related data links and the utilization of one data link for recovery of errors detected on another link'
[patent_app_type] => 1
[patent_app_number] => 8/979044
[patent_app_country] => US
[patent_app_date] => 1997-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4144
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/049/06049902.pdf
[firstpage_image] =>[orig_patent_app_number] => 979044
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979044 | Method and system in a data communications system for the establishment of multiple, related data links and the utilization of one data link for recovery of errors detected on another link | Nov 25, 1997 | Issued |
Array
(
[id] => 3959615
[patent_doc_number] => 05991158
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Slot for mechanically detecting the presence of a computer card'
[patent_app_type] => 1
[patent_app_number] => 8/979045
[patent_app_country] => US
[patent_app_date] => 1997-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2374
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/991/05991158.pdf
[firstpage_image] =>[orig_patent_app_number] => 979045
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979045 | Slot for mechanically detecting the presence of a computer card | Nov 25, 1997 | Issued |
Array
(
[id] => 4240617
[patent_doc_number] => 06012161
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'System and method for joint coding and decision feedback equalization'
[patent_app_type] => 1
[patent_app_number] => 8/979982
[patent_app_country] => US
[patent_app_date] => 1997-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 6367
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/012/06012161.pdf
[firstpage_image] =>[orig_patent_app_number] => 979982
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979982 | System and method for joint coding and decision feedback equalization | Nov 25, 1997 | Issued |
Array
(
[id] => 3962707
[patent_doc_number] => 05974584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Parity checking in a real-time digital communications system'
[patent_app_type] => 1
[patent_app_number] => 8/974966
[patent_app_country] => US
[patent_app_date] => 1997-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5053
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/974/05974584.pdf
[firstpage_image] =>[orig_patent_app_number] => 974966
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/974966 | Parity checking in a real-time digital communications system | Nov 19, 1997 | Issued |
Array
(
[id] => 3938451
[patent_doc_number] => 05946328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Method and means for efficient error detection and correction in long byte strings using integrated interleaved Reed-Solomon codewords'
[patent_app_type] => 1
[patent_app_number] => 8/971796
[patent_app_country] => US
[patent_app_date] => 1997-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6164
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 312
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/946/05946328.pdf
[firstpage_image] =>[orig_patent_app_number] => 971796
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/971796 | Method and means for efficient error detection and correction in long byte strings using integrated interleaved Reed-Solomon codewords | Nov 16, 1997 | Issued |
Array
(
[id] => 3988255
[patent_doc_number] => 05917731
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Process for detecting complete sequences and failed sequences in a situation recognition sequence'
[patent_app_type] => 1
[patent_app_number] => 8/970618
[patent_app_country] => US
[patent_app_date] => 1997-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4873
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/917/05917731.pdf
[firstpage_image] =>[orig_patent_app_number] => 970618
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/970618 | Process for detecting complete sequences and failed sequences in a situation recognition sequence | Nov 13, 1997 | Issued |
Array
(
[id] => 3915343
[patent_doc_number] => 05951624
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Computer system to compress pixel bits'
[patent_app_type] => 1
[patent_app_number] => 8/969129
[patent_app_country] => US
[patent_app_date] => 1997-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 3633
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/951/05951624.pdf
[firstpage_image] =>[orig_patent_app_number] => 969129
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/969129 | Computer system to compress pixel bits | Nov 11, 1997 | Issued |
Array
(
[id] => 4034250
[patent_doc_number] => 05926404
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Computer system with unattended operation power-saving suspend mode'
[patent_app_type] => 1
[patent_app_number] => 8/968383
[patent_app_country] => US
[patent_app_date] => 1997-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 1
[patent_no_of_words] => 5209
[patent_no_of_claims] => 53
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926404.pdf
[firstpage_image] =>[orig_patent_app_number] => 968383
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/968383 | Computer system with unattended operation power-saving suspend mode | Nov 11, 1997 | Issued |
Array
(
[id] => 3976238
[patent_doc_number] => 05890799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Method for reducing power consumption in a portable electronic device with a liquid crystal display screen'
[patent_app_type] => 1
[patent_app_number] => 8/966831
[patent_app_country] => US
[patent_app_date] => 1997-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2177
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/890/05890799.pdf
[firstpage_image] =>[orig_patent_app_number] => 966831
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/966831 | Method for reducing power consumption in a portable electronic device with a liquid crystal display screen | Nov 9, 1997 | Issued |
Array
(
[id] => 4374505
[patent_doc_number] => 06202181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
[patent_title] => 'Method for diagnosing bridging faults in integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/962711
[patent_app_country] => US
[patent_app_date] => 1997-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 17341
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/202/06202181.pdf
[firstpage_image] =>[orig_patent_app_number] => 962711
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/962711 | Method for diagnosing bridging faults in integrated circuits | Nov 2, 1997 | Issued |
Array
(
[id] => 3966219
[patent_doc_number] => 05983256
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Apparatus for performing multiply-add operations on packed data'
[patent_app_type] => 1
[patent_app_number] => 8/960413
[patent_app_country] => US
[patent_app_date] => 1997-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 8662
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/983/05983256.pdf
[firstpage_image] =>[orig_patent_app_number] => 960413
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/960413 | Apparatus for performing multiply-add operations on packed data | Oct 28, 1997 | Issued |
Array
(
[id] => 4152613
[patent_doc_number] => 06035430
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Semiconductor integrated circuit device with restoring circuit'
[patent_app_type] => 1
[patent_app_number] => 8/954098
[patent_app_country] => US
[patent_app_date] => 1997-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4701
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/035/06035430.pdf
[firstpage_image] =>[orig_patent_app_number] => 954098
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/954098 | Semiconductor integrated circuit device with restoring circuit | Oct 19, 1997 | Issued |
Array
(
[id] => 4054383
[patent_doc_number] => 05875124
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'Full adder circuit'
[patent_app_type] => 1
[patent_app_number] => 8/950108
[patent_app_country] => US
[patent_app_date] => 1997-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 15356
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/875/05875124.pdf
[firstpage_image] =>[orig_patent_app_number] => 950108
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/950108 | Full adder circuit | Oct 15, 1997 | Issued |
Array
(
[id] => 4267001
[patent_doc_number] => RE037048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Field programmable digital signal processing array integrated circuit'
[patent_app_type] => 2
[patent_app_number] => 8/946928
[patent_app_country] => US
[patent_app_date] => 1997-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 8688
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/037/RE037048.pdf
[firstpage_image] =>[orig_patent_app_number] => 946928
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/946928 | Field programmable digital signal processing array integrated circuit | Oct 7, 1997 | Issued |
Array
(
[id] => 4038344
[patent_doc_number] => 05903486
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Device for digitally carrying out a division operation'
[patent_app_type] => 1
[patent_app_number] => 8/944707
[patent_app_country] => US
[patent_app_date] => 1997-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 7900
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 319
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/903/05903486.pdf
[firstpage_image] =>[orig_patent_app_number] => 944707
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/944707 | Device for digitally carrying out a division operation | Oct 5, 1997 | Issued |
Array
(
[id] => 4152677
[patent_doc_number] => 06035435
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Method and apparatus for encoding a binary signal'
[patent_app_type] => 1
[patent_app_number] => 8/940869
[patent_app_country] => US
[patent_app_date] => 1997-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 9691
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/035/06035435.pdf
[firstpage_image] =>[orig_patent_app_number] => 940869
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/940869 | Method and apparatus for encoding a binary signal | Sep 29, 1997 | Issued |