
Amir Alavi
Examiner (ID: 2290, Phone: (571)272-7386 , Office: P/2668 )
| Most Active Art Unit | 2668 |
| Art Unit(s) | 2621, 2668, 2624, 2721 |
| Total Applications | 2256 |
| Issued Applications | 2054 |
| Pending Applications | 121 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20388202
[patent_doc_number] => 12487928
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-02
[patent_title] => Two-stage cache partitioning
[patent_app_type] => utility
[patent_app_number] => 17/711471
[patent_app_country] => US
[patent_app_date] => 2022-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 11060
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711471
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/711471 | Two-stage cache partitioning | Mar 31, 2022 | Issued |
Array
(
[id] => 18966216
[patent_doc_number] => 11899985
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-02-13
[patent_title] => Virtual modules in TCAM
[patent_app_type] => utility
[patent_app_number] => 17/710840
[patent_app_country] => US
[patent_app_date] => 2022-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5651
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710840
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/710840 | Virtual modules in TCAM | Mar 30, 2022 | Issued |
Array
(
[id] => 18677983
[patent_doc_number] => 20230315630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICY
[patent_app_type] => utility
[patent_app_number] => 17/708435
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9204
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708435
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/708435 | DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICY | Mar 29, 2022 | Pending |
Array
(
[id] => 17736539
[patent_doc_number] => 20220221998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => MEMORY MANAGEMENT METHOD, ELECTRONIC DEVICE AND NON-TRANSITORY COMPUTER-READABLE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 17/706485
[patent_app_country] => US
[patent_app_date] => 2022-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11889
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706485
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/706485 | MEMORY MANAGEMENT METHOD, ELECTRONIC DEVICE AND NON-TRANSITORY COMPUTER-READABLE MEDIUM | Mar 27, 2022 | Abandoned |
Array
(
[id] => 18949655
[patent_doc_number] => 11892948
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => System-on-a-chip (SoC) based fast path enabler for data applications
[patent_app_type] => utility
[patent_app_number] => 17/705334
[patent_app_country] => US
[patent_app_date] => 2022-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3993
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705334
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/705334 | System-on-a-chip (SoC) based fast path enabler for data applications | Mar 26, 2022 | Issued |
Array
(
[id] => 18694904
[patent_doc_number] => 20230325322
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => CACHING SYSTEM AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/705149
[patent_app_country] => US
[patent_app_date] => 2022-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11389
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705149
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/705149 | Caching system and method | Mar 24, 2022 | Issued |
Array
(
[id] => 19137164
[patent_doc_number] => 11972127
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-30
[patent_title] => Memory system executing background operation using external device and operation method thereof
[patent_app_type] => utility
[patent_app_number] => 17/701189
[patent_app_country] => US
[patent_app_date] => 2022-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10144
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701189
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/701189 | Memory system executing background operation using external device and operation method thereof | Mar 21, 2022 | Issued |
Array
(
[id] => 19293120
[patent_doc_number] => 12032472
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Physical memory address omission or obfuscation within an execution trace
[patent_app_type] => utility
[patent_app_number] => 18/548198
[patent_app_country] => US
[patent_app_date] => 2022-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 17559
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548198
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/548198 | Physical memory address omission or obfuscation within an execution trace | Mar 20, 2022 | Issued |
Array
(
[id] => 17884951
[patent_doc_number] => 20220300428
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer between a Host System and a Memory Sub-System
[patent_app_type] => utility
[patent_app_number] => 17/685250
[patent_app_country] => US
[patent_app_date] => 2022-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11980
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685250
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/685250 | Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system | Mar 1, 2022 | Issued |
Array
(
[id] => 18561665
[patent_doc_number] => 11726908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-15
[patent_title] => Garbage collection in a memory sub-system during a low battery state
[patent_app_type] => utility
[patent_app_number] => 17/672872
[patent_app_country] => US
[patent_app_date] => 2022-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7813
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672872
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/672872 | Garbage collection in a memory sub-system during a low battery state | Feb 15, 2022 | Issued |
Array
(
[id] => 18454304
[patent_doc_number] => 20230195584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => LIFECYCLE MANAGEMENT OF VIRTUAL INFRASTRUCTURE MANAGEMENT SERVER APPLIANCE
[patent_app_type] => utility
[patent_app_number] => 17/670544
[patent_app_country] => US
[patent_app_date] => 2022-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4052
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670544
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/670544 | Lifecycle management of virtual infrastructure management server appliance | Feb 13, 2022 | Issued |
Array
(
[id] => 17613921
[patent_doc_number] => 20220156201
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => MAPPING NON-TYPED MEMORY ACCESS TO TYPED MEMORY ACCESS
[patent_app_type] => utility
[patent_app_number] => 17/665823
[patent_app_country] => US
[patent_app_date] => 2022-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24329
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665823
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/665823 | Mapping non-typed memory access to typed memory access | Feb 6, 2022 | Issued |
Array
(
[id] => 18266786
[patent_doc_number] => 20230088028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/590322
[patent_app_country] => US
[patent_app_date] => 2022-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6306
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590322
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/590322 | Memory system | Jan 31, 2022 | Issued |
Array
(
[id] => 19122754
[patent_doc_number] => 11966743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-23
[patent_title] => Reverse order queue updates by virtual devices
[patent_app_type] => utility
[patent_app_number] => 17/586385
[patent_app_country] => US
[patent_app_date] => 2022-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 13589
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586385
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/586385 | Reverse order queue updates by virtual devices | Jan 26, 2022 | Issued |
Array
(
[id] => 17809333
[patent_doc_number] => 20220261168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => INFINITE MEMORY FABRIC HARDWARE IMPLEMENTATION WITH ROUTER
[patent_app_type] => utility
[patent_app_number] => 17/582416
[patent_app_country] => US
[patent_app_date] => 2022-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582416
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/582416 | Infinite memory fabric hardware implementation with router | Jan 23, 2022 | Issued |
Array
(
[id] => 19458955
[patent_doc_number] => 12099444
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-24
[patent_title] => Cat aware loads and software prefetches
[patent_app_type] => utility
[patent_app_number] => 17/581616
[patent_app_country] => US
[patent_app_date] => 2022-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 7039
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581616
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/581616 | Cat aware loads and software prefetches | Jan 20, 2022 | Issued |
Array
(
[id] => 17581254
[patent_doc_number] => 20220138109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => CONTINUOUS READ WITH MULTIPLE READ COMMANDS
[patent_app_type] => utility
[patent_app_number] => 17/579428
[patent_app_country] => US
[patent_app_date] => 2022-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10865
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579428
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/579428 | Continuous read with multiple read commands | Jan 18, 2022 | Issued |
Array
(
[id] => 17763514
[patent_doc_number] => 20220237126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => PAGE TABLE MANAGER
[patent_app_type] => utility
[patent_app_number] => 17/576398
[patent_app_country] => US
[patent_app_date] => 2022-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576398
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/576398 | Page table manager | Jan 13, 2022 | Issued |
Array
(
[id] => 18780742
[patent_doc_number] => 11822472
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => Memory management unit for multi-threaded architecture
[patent_app_type] => utility
[patent_app_number] => 17/575521
[patent_app_country] => US
[patent_app_date] => 2022-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 10053
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575521
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/575521 | Memory management unit for multi-threaded architecture | Jan 12, 2022 | Issued |
Array
(
[id] => 19061687
[patent_doc_number] => 11940921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => Bounding box prefetcher
[patent_app_type] => utility
[patent_app_number] => 17/570452
[patent_app_country] => US
[patent_app_date] => 2022-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 13259
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570452
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/570452 | Bounding box prefetcher | Jan 6, 2022 | Issued |