Search

Amir Zarabian

Supervisory Patent Examiner (ID: 2365, Phone: (571)272-1852 , Office: P/2827 )

Most Active Art Unit
2511
Art Unit(s)
2602, 2818, 2822, 2511, 2827, 2824, 2502
Total Applications
1127
Issued Applications
976
Pending Applications
27
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4171304 [patent_doc_number] => 06115280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Semiconductor memory capable of burst operation' [patent_app_type] => 1 [patent_app_number] => 8/833178 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12667 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115280.pdf [firstpage_image] =>[orig_patent_app_number] => 833178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/833178
Semiconductor memory capable of burst operation Apr 3, 1997 Issued
Array ( [id] => 4015221 [patent_doc_number] => 05859805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Dynamic semiconductor memory device having an improved sense amplifier layout arrangement' [patent_app_type] => 1 [patent_app_number] => 8/832818 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 6265 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859805.pdf [firstpage_image] =>[orig_patent_app_number] => 832818 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/832818
Dynamic semiconductor memory device having an improved sense amplifier layout arrangement Apr 3, 1997 Issued
Array ( [id] => 3993898 [patent_doc_number] => 05949712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Non-volatile memory array using gate breakdown structure' [patent_app_type] => 1 [patent_app_number] => 8/826456 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 7631 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949712.pdf [firstpage_image] =>[orig_patent_app_number] => 826456 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826456
Non-volatile memory array using gate breakdown structure Mar 26, 1997 Issued
Array ( [id] => 3998025 [patent_doc_number] => 05959885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Non-volatile memory array using single poly EEPROM in standard CMOS process' [patent_app_type] => 1 [patent_app_number] => 8/828151 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 7640 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959885.pdf [firstpage_image] =>[orig_patent_app_number] => 828151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/828151
Non-volatile memory array using single poly EEPROM in standard CMOS process Mar 26, 1997 Issued
Array ( [id] => 3950727 [patent_doc_number] => 05930189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor memory device having short read time' [patent_app_type] => 1 [patent_app_number] => 8/824611 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4219 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930189.pdf [firstpage_image] =>[orig_patent_app_number] => 824611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824611
Semiconductor memory device having short read time Mar 26, 1997 Issued
Array ( [id] => 3770437 [patent_doc_number] => 05852575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Apparatus and method for reading multi-level data stored in a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/819052 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 55 [patent_no_of_words] => 19694 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852575.pdf [firstpage_image] =>[orig_patent_app_number] => 819052 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819052
Apparatus and method for reading multi-level data stored in a semiconductor memory Mar 17, 1997 Issued
Array ( [id] => 3830625 [patent_doc_number] => 05790463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'On-chip mobile ion contamination test circuit' [patent_app_type] => 1 [patent_app_number] => 8/814778 [patent_app_country] => US [patent_app_date] => 1997-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2167 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790463.pdf [firstpage_image] =>[orig_patent_app_number] => 814778 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/814778
On-chip mobile ion contamination test circuit Mar 9, 1997 Issued
Array ( [id] => 3706912 [patent_doc_number] => 05677884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Circuit for cancelling and replacing redundant elements' [patent_app_type] => 1 [patent_app_number] => 8/816203 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3673 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677884.pdf [firstpage_image] =>[orig_patent_app_number] => 816203 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816203
Circuit for cancelling and replacing redundant elements Feb 27, 1997 Issued
Array ( [id] => 3896390 [patent_doc_number] => 05894442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Semiconductor memory device equipped with an equalizing control circuit having a function of latching an equalizing signal' [patent_app_type] => 1 [patent_app_number] => 8/805614 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3354 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894442.pdf [firstpage_image] =>[orig_patent_app_number] => 805614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805614
Semiconductor memory device equipped with an equalizing control circuit having a function of latching an equalizing signal Feb 25, 1997 Issued
Array ( [id] => 3888656 [patent_doc_number] => 05764569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Test structure and method to characterize charge gain in a non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/806057 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5093 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764569.pdf [firstpage_image] =>[orig_patent_app_number] => 806057 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806057
Test structure and method to characterize charge gain in a non-volatile memory Feb 24, 1997 Issued
Array ( [id] => 3993735 [patent_doc_number] => 05862077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Fast sensing amplifier for flash memory' [patent_app_type] => 1 [patent_app_number] => 8/804951 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4206 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862077.pdf [firstpage_image] =>[orig_patent_app_number] => 804951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804951
Fast sensing amplifier for flash memory Feb 23, 1997 Issued
Array ( [id] => 3960178 [patent_doc_number] => 05991195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Flash EEPROM with erase verification and address scrambling architecture' [patent_app_type] => 1 [patent_app_number] => 8/803397 [patent_app_country] => US [patent_app_date] => 1997-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 5360 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991195.pdf [firstpage_image] =>[orig_patent_app_number] => 803397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803397
Flash EEPROM with erase verification and address scrambling architecture Feb 19, 1997 Issued
Array ( [id] => 3789932 [patent_doc_number] => 05757693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Gain memory cell with diode' [patent_app_type] => 1 [patent_app_number] => 8/803056 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757693.pdf [firstpage_image] =>[orig_patent_app_number] => 803056 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803056
Gain memory cell with diode Feb 18, 1997 Issued
Array ( [id] => 3844349 [patent_doc_number] => 05761114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Multi-level storage gain cell with stepline' [patent_app_type] => 1 [patent_app_number] => 8/803034 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761114.pdf [firstpage_image] =>[orig_patent_app_number] => 803034 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803034
Multi-level storage gain cell with stepline Feb 18, 1997 Issued
Array ( [id] => 3962380 [patent_doc_number] => 05956285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Synchronous semiconductor memory device with multi-bank configuration' [patent_app_type] => 1 [patent_app_number] => 8/798953 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 17229 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956285.pdf [firstpage_image] =>[orig_patent_app_number] => 798953 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798953
Synchronous semiconductor memory device with multi-bank configuration Feb 10, 1997 Issued
Array ( [id] => 4054839 [patent_doc_number] => 05875149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Word line driver for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/828817 [patent_app_country] => US [patent_app_date] => 1997-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3801 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875149.pdf [firstpage_image] =>[orig_patent_app_number] => 828817 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/828817
Word line driver for semiconductor memories Feb 5, 1997 Issued
Array ( [id] => 3882952 [patent_doc_number] => 05838620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Circuit for cancelling and replacing redundant elements' [patent_app_type] => 1 [patent_app_number] => 8/796148 [patent_app_country] => US [patent_app_date] => 1997-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3673 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838620.pdf [firstpage_image] =>[orig_patent_app_number] => 796148 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/796148
Circuit for cancelling and replacing redundant elements Feb 5, 1997 Issued
Array ( [id] => 4202443 [patent_doc_number] => 06154410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method and apparatus for reducing antifuse programming time' [patent_app_type] => 1 [patent_app_number] => 8/795531 [patent_app_country] => US [patent_app_date] => 1997-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1863 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154410.pdf [firstpage_image] =>[orig_patent_app_number] => 795531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795531
Method and apparatus for reducing antifuse programming time Feb 4, 1997 Issued
Array ( [id] => 4054784 [patent_doc_number] => 05875145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation' [patent_app_type] => 1 [patent_app_number] => 8/795529 [patent_app_country] => US [patent_app_date] => 1997-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 8974 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875145.pdf [firstpage_image] =>[orig_patent_app_number] => 795529 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795529
Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation Feb 4, 1997 Issued
Array ( [id] => 3697164 [patent_doc_number] => 05696716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Programmable memory element' [patent_app_type] => 1 [patent_app_number] => 8/794965 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2535 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696716.pdf [firstpage_image] =>[orig_patent_app_number] => 794965 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794965
Programmable memory element Feb 3, 1997 Issued
Menu