| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05784323
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[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Test converage of embedded memories on semiconductor substrates'
[patent_app_type] => 1
[patent_app_number] => 8/795367
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Array
(
[id] => 3789285
[patent_doc_number] => 05808944
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Semiconductor memory device having a defect relief arrangement'
[patent_app_type] => 1
[patent_app_number] => 8/797654
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[firstpage_image] =>[orig_patent_app_number] => 797654
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Array
(
[id] => 4017368
[patent_doc_number] => 06005796
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Single ended simpler dual port memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/789300
[patent_app_country] => US
[patent_app_date] => 1997-01-30
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[firstpage_image] =>[orig_patent_app_number] => 789300
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/789300 | Single ended simpler dual port memory cell | Jan 29, 1997 | Issued |
Array
(
[id] => 4017354
[patent_doc_number] => 06005795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Single ended dual port memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/789299
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[patent_app_date] => 1997-01-30
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[firstpage_image] =>[orig_patent_app_number] => 789299
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/789299 | Single ended dual port memory cell | Jan 29, 1997 | Issued |
Array
(
[id] => 3742099
[patent_doc_number] => 05694369
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/790626
[patent_app_country] => US
[patent_app_date] => 1997-01-29
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[firstpage_image] =>[orig_patent_app_number] => 790626
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/790626 | Semiconductor memory device | Jan 28, 1997 | Issued |
| 90/004531 | DRAM CELL UTILIZING NOVEL CAPACITOR | Jan 27, 1997 | Issued |
Array
(
[id] => 4061304
[patent_doc_number] => 05870348
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Dynamic semiconductor memory device having excellent charge retention characteristics'
[patent_app_type] => 1
[patent_app_number] => 8/789240
[patent_app_country] => US
[patent_app_date] => 1997-01-28
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[firstpage_image] =>[orig_patent_app_number] => 789240
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/789240 | Dynamic semiconductor memory device having excellent charge retention characteristics | Jan 27, 1997 | Issued |
| 08/788556 | STATIC RANDOM ACCESS MEMORY CELL UTILIZING DRIVE TRANSISTORS WITH LOW THRESHOLD VOLTAGE | Jan 23, 1997 | Abandoned |
Array
(
[id] => 3741891
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[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Memory cell and wordline driver for embedded DRAM in ASIC process'
[patent_app_type] => 1
[patent_app_number] => 8/786922
[patent_app_country] => US
[patent_app_date] => 1997-01-23
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[pdf_file] => patents/05/694/05694355.pdf
[firstpage_image] =>[orig_patent_app_number] => 786922
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/786922 | Memory cell and wordline driver for embedded DRAM in ASIC process | Jan 22, 1997 | Issued |
Array
(
[id] => 3808021
[patent_doc_number] => 05781495
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Semiconductor memory device for multi-bit or multi-bank architectures'
[patent_app_type] => 1
[patent_app_number] => 8/787483
[patent_app_country] => US
[patent_app_date] => 1997-01-22
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[pdf_file] => patents/05/781/05781495.pdf
[firstpage_image] =>[orig_patent_app_number] => 787483
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/787483 | Semiconductor memory device for multi-bit or multi-bank architectures | Jan 21, 1997 | Issued |
Array
(
[id] => 3900755
[patent_doc_number] => 05777928
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Multi-port register'
[patent_app_type] => 1
[patent_app_number] => 8/785575
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[firstpage_image] =>[orig_patent_app_number] => 785575
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/785575 | Multi-port register | Jan 20, 1997 | Issued |
Array
(
[id] => 3970844
[patent_doc_number] => 05901079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Skewed memory cell apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 8/782723
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 782723
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/782723 | Skewed memory cell apparatus and method | Jan 12, 1997 | Issued |
Array
(
[id] => 4010490
[patent_doc_number] => 05923585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Source biasing in non-volatile memory having row-based sectors'
[patent_app_type] => 1
[patent_app_number] => 8/781741
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[patent_app_date] => 1997-01-10
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[firstpage_image] =>[orig_patent_app_number] => 781741
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/781741 | Source biasing in non-volatile memory having row-based sectors | Jan 9, 1997 | Issued |
Array
(
[id] => 3825338
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[patent_issue_date] => 1998-09-22
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[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/781013 | Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal | Jan 9, 1997 | Issued |
Array
(
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Array
(
[id] => 3837738
[patent_doc_number] => 05784325
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[patent_kind] => NA
[patent_issue_date] => 1998-07-21
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[firstpage_image] =>[orig_patent_app_number] => 779115
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/779115 | Semiconductor nonvolatile memory device | Jan 5, 1997 | Issued |
Array
(
[id] => 3830518
[patent_doc_number] => 05790455
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[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Low voltage single supply CMOS electrically erasable read-only memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/778315 | Low voltage single supply CMOS electrically erasable read-only memory | Jan 1, 1997 | Issued |
Array
(
[id] => 3892689
[patent_doc_number] => 05748556
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Tristatable driver for internal data bus lines'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777836 | Tristatable driver for internal data bus lines | Dec 30, 1996 | Issued |
Array
(
[id] => 3825069
[patent_doc_number] => 05812469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Method and apparatus for testing multi-port memory'
[patent_app_type] => 1
[patent_app_number] => 8/775856
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/775856 | Method and apparatus for testing multi-port memory | Dec 30, 1996 | Issued |
| 08/775110 | METHOD OF AVOIDING DISTURBANCE DURING THE STEP OF PROGRAMMING AND ERASING AN ELECTRICALLY PROGRAMMABLE, SEMICONDUCTOR NON-VOLATILE STORAGE DEVICE | Dec 29, 1996 | Abandoned |