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Amir Zarabian

Supervisory Patent Examiner (ID: 13021, Phone: (571)272-1852 , Office: P/2827 )

Most Active Art Unit
2511
Art Unit(s)
2824, 2602, 2822, 2502, 2511, 2818, 2827
Total Applications
1128
Issued Applications
976
Pending Applications
28
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3897798 [patent_doc_number] => 05715204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Sense amplifier with hysteresis' [patent_app_type] => 1 [patent_app_number] => 8/432838 [patent_app_country] => US [patent_app_date] => 1995-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3214 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715204.pdf [firstpage_image] =>[orig_patent_app_number] => 432838 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/432838
Sense amplifier with hysteresis May 1, 1995 Issued
Array ( [id] => 4266212 [patent_doc_number] => 06208574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Sense amplifier with local column read amplifier and local data write drivers' [patent_app_type] => 1 [patent_app_number] => 8/432884 [patent_app_country] => US [patent_app_date] => 1995-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7618 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208574.pdf [firstpage_image] =>[orig_patent_app_number] => 432884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/432884
Sense amplifier with local column read amplifier and local data write drivers May 1, 1995 Issued
Array ( [id] => 3892242 [patent_doc_number] => 05805513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor' [patent_app_type] => 1 [patent_app_number] => 8/432867 [patent_app_country] => US [patent_app_date] => 1995-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 133 [patent_figures_cnt] => 145 [patent_no_of_words] => 43486 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805513.pdf [firstpage_image] =>[orig_patent_app_number] => 432867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/432867
Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor May 1, 1995 Issued
Array ( [id] => 3600336 [patent_doc_number] => 05586075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Electrically erasable and programmable read-only memory having redundant memory cell row' [patent_app_type] => 1 [patent_app_number] => 8/429901 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5907 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586075.pdf [firstpage_image] =>[orig_patent_app_number] => 429901 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/429901
Electrically erasable and programmable read-only memory having redundant memory cell row Apr 26, 1995 Issued
Array ( [id] => 3608523 [patent_doc_number] => 05559734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Multiple voltage memory' [patent_app_type] => 1 [patent_app_number] => 8/427570 [patent_app_country] => US [patent_app_date] => 1995-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 3838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559734.pdf [firstpage_image] =>[orig_patent_app_number] => 427570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/427570
Multiple voltage memory Apr 23, 1995 Issued
Array ( [id] => 4077920 [patent_doc_number] => 06009013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Contactless array configuration for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/426685 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5454 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009013.pdf [firstpage_image] =>[orig_patent_app_number] => 426685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426685
Contactless array configuration for semiconductor memories Apr 20, 1995 Issued
Array ( [id] => 4077920 [patent_doc_number] => 06009013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Contactless array configuration for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/426685 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5454 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009013.pdf [firstpage_image] =>[orig_patent_app_number] => 426685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426685
Contactless array configuration for semiconductor memories Apr 20, 1995 Issued
Array ( [id] => 4077920 [patent_doc_number] => 06009013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Contactless array configuration for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/426685 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5454 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009013.pdf [firstpage_image] =>[orig_patent_app_number] => 426685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426685
Contactless array configuration for semiconductor memories Apr 20, 1995 Issued
Array ( [id] => 4077920 [patent_doc_number] => 06009013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Contactless array configuration for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/426685 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5454 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009013.pdf [firstpage_image] =>[orig_patent_app_number] => 426685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426685
Contactless array configuration for semiconductor memories Apr 20, 1995 Issued
Array ( [id] => 3836098 [patent_doc_number] => 05732024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Circuits, systems and methods for modifying data stored in a memory using logic operations' [patent_app_type] => 1 [patent_app_number] => 8/424653 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7849 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732024.pdf [firstpage_image] =>[orig_patent_app_number] => 424653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/424653
Circuits, systems and methods for modifying data stored in a memory using logic operations Apr 18, 1995 Issued
Array ( [id] => 3601489 [patent_doc_number] => 05568435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Circuit for SRAM test mode isolated bitline modulation' [patent_app_type] => 1 [patent_app_number] => 8/421506 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568435.pdf [firstpage_image] =>[orig_patent_app_number] => 421506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/421506
Circuit for SRAM test mode isolated bitline modulation Apr 11, 1995 Issued
Array ( [id] => 3727585 [patent_doc_number] => 05617357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Flash EEPROM memory with improved discharge speed using substrate bias and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/420989 [patent_app_country] => US [patent_app_date] => 1995-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6970 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617357.pdf [firstpage_image] =>[orig_patent_app_number] => 420989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/420989
Flash EEPROM memory with improved discharge speed using substrate bias and method therefor Apr 6, 1995 Issued
08/418403 HIGH VOLTAGE BOOSTED WORD LINE SUPPLY CHARGE PUMP AND REGULATOR FOR DRAM Apr 6, 1995 Abandoned
08/416967 HIERARCHICAL MEMORY ARRAY STRUCTURE HAVING ELECTRICALLY ISOLATED BIT LINES Apr 4, 1995 Abandoned
08/416664 SEMICONDUCTOR MEMORY DEVICE UTILIZING TWO DATA LINE PAIRS AND REALIZING HIGH-SPEED DATA READOUT Apr 4, 1995 Abandoned
08/417007 CIRCUIT FOR CANCELLING AND REPLACING REDUNDANT ELEMENTS Apr 4, 1995 Abandoned
08/413969 PROGRAMMABLE MEMORY ELEMENT Mar 30, 1995 Abandoned
Array ( [id] => 3622580 [patent_doc_number] => 05566113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Semiconductor memory circuit having verify mode' [patent_app_type] => 1 [patent_app_number] => 8/412864 [patent_app_country] => US [patent_app_date] => 1995-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 10815 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566113.pdf [firstpage_image] =>[orig_patent_app_number] => 412864 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/412864
Semiconductor memory circuit having verify mode Mar 28, 1995 Issued
08/408252 SEMICONDUCTOR MEMORY DEVICE HAVING CIRCUIT FOR ACTIVATING PREDETERMINED ROWS OF MEMORY CELLS UPON DETECTION OF DISTURB REFRESH TEST Mar 21, 1995 Abandoned
Array ( [id] => 3563610 [patent_doc_number] => 05519659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test' [patent_app_type] => 1 [patent_app_number] => 8/408256 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 37 [patent_no_of_words] => 12849 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519659.pdf [firstpage_image] =>[orig_patent_app_number] => 408256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/408256
Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test Mar 21, 1995 Issued
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