| Application number | Title of the application | Filing Date | Status |
|---|
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Array
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[patent_title] => 'Sense amplifier with local column read amplifier and local data write drivers'
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Array
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[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/432867
[patent_app_country] => US
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Array
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[patent_doc_number] => 05586075
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[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Electrically erasable and programmable read-only memory having redundant memory cell row'
[patent_app_type] => 1
[patent_app_number] => 8/429901
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[patent_app_date] => 1995-04-27
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Array
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[patent_issue_date] => 1996-09-24
[patent_title] => 'Multiple voltage memory'
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Array
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Array
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[patent_kind] => NA
[patent_issue_date] => 1998-03-24
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[patent_app_type] => 1
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Array
(
[id] => 3601489
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Circuit for SRAM test mode isolated bitline modulation'
[patent_app_type] => 1
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Array
(
[id] => 3727585
[patent_doc_number] => 05617357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-01
[patent_title] => 'Flash EEPROM memory with improved discharge speed using substrate bias and method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/420989
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| 08/418403 | HIGH VOLTAGE BOOSTED WORD LINE SUPPLY CHARGE PUMP AND REGULATOR FOR DRAM | Apr 6, 1995 | Abandoned |
| 08/416967 | HIERARCHICAL MEMORY ARRAY STRUCTURE HAVING ELECTRICALLY ISOLATED BIT LINES | Apr 4, 1995 | Abandoned |
| 08/416664 | SEMICONDUCTOR MEMORY DEVICE UTILIZING TWO DATA LINE PAIRS AND REALIZING HIGH-SPEED DATA READOUT | Apr 4, 1995 | Abandoned |
| 08/417007 | CIRCUIT FOR CANCELLING AND REPLACING REDUNDANT ELEMENTS | Apr 4, 1995 | Abandoned |
| 08/413969 | PROGRAMMABLE MEMORY ELEMENT | Mar 30, 1995 | Abandoned |
Array
(
[id] => 3622580
[patent_doc_number] => 05566113
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Semiconductor memory circuit having verify mode'
[patent_app_type] => 1
[patent_app_number] => 8/412864
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/412864 | Semiconductor memory circuit having verify mode | Mar 28, 1995 | Issued |
| 08/408252 | SEMICONDUCTOR MEMORY DEVICE HAVING CIRCUIT FOR ACTIVATING PREDETERMINED ROWS OF MEMORY CELLS UPON DETECTION OF DISTURB REFRESH TEST | Mar 21, 1995 | Abandoned |
Array
(
[id] => 3563610
[patent_doc_number] => 05519659
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/408256 | Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test | Mar 21, 1995 | Issued |