| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test'
[patent_app_type] => 1
[patent_app_number] => 8/408255
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| 08/406656 | SEMICONDUCTOR INTEGRATED CIRCUIT APPLICABLE TO DATA READ CIRCUIT FROM MEMORY | Mar 19, 1995 | Abandoned |
| 08/405672 | SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY SERIAL ACCESS MEMORY PORTION | Mar 16, 1995 | Abandoned |
Array
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[patent_doc_number] => 05610859
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[patent_issue_date] => 1997-03-11
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Array
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[patent_doc_number] => 05546349
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[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Exchangeable hierarchical data line structure'
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Array
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[patent_doc_number] => 05535164
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[patent_kind] => NA
[patent_issue_date] => 1996-07-09
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Array
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Array
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[patent_issue_date] => 1997-07-29
[patent_title] => 'Burst EDO memory device having pipelined output buffer'
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Array
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[id] => 3602817
[patent_doc_number] => 05521864
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/385866 | Non-volatile semiconductor memory device allowing fast verifying operation | Feb 8, 1995 | Issued |
| 08/385470 | SEMICONDUCTOR MEMORY DEVICE HAVING A MEMORY CELL CAPACITOR AND A FABRICATION PROCESS THEREOF | Feb 7, 1995 | Abandoned |
Array
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[patent_issue_date] => 1996-08-06
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