Search

Amir Zarabian

Supervisory Patent Examiner (ID: 13021, Phone: (571)272-1852 , Office: P/2827 )

Most Active Art Unit
2511
Art Unit(s)
2824, 2602, 2822, 2502, 2511, 2818, 2827
Total Applications
1128
Issued Applications
976
Pending Applications
28
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3563192 [patent_doc_number] => 05574691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test' [patent_app_type] => 1 [patent_app_number] => 8/408255 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 37 [patent_no_of_words] => 12855 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574691.pdf [firstpage_image] =>[orig_patent_app_number] => 408255 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/408255
Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test Mar 21, 1995 Issued
08/406656 SEMICONDUCTOR INTEGRATED CIRCUIT APPLICABLE TO DATA READ CIRCUIT FROM MEMORY Mar 19, 1995 Abandoned
08/405672 SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY SERIAL ACCESS MEMORY PORTION Mar 16, 1995 Abandoned
Array ( [id] => 3644635 [patent_doc_number] => 05610859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/404572 [patent_app_country] => US [patent_app_date] => 1995-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 176 [patent_no_of_words] => 17556 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610859.pdf [firstpage_image] =>[orig_patent_app_number] => 404572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/404572
Semiconductor memory device Mar 14, 1995 Issued
Array ( [id] => 3558145 [patent_doc_number] => 05546349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Exchangeable hierarchical data line structure' [patent_app_type] => 1 [patent_app_number] => 8/403265 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10106 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546349.pdf [firstpage_image] =>[orig_patent_app_number] => 403265 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403265
Exchangeable hierarchical data line structure Mar 12, 1995 Issued
Array ( [id] => 3623400 [patent_doc_number] => 05535164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'BIST tester for multiple memories' [patent_app_type] => 1 [patent_app_number] => 8/398468 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535164.pdf [firstpage_image] =>[orig_patent_app_number] => 398468 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/398468
BIST tester for multiple memories Mar 2, 1995 Issued
Array ( [id] => 3520989 [patent_doc_number] => 05563833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Using one memory to supply addresses to an associated memory during testing' [patent_app_type] => 1 [patent_app_number] => 8/398465 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5296 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563833.pdf [firstpage_image] =>[orig_patent_app_number] => 398465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/398465
Using one memory to supply addresses to an associated memory during testing Mar 2, 1995 Issued
Array ( [id] => 3873241 [patent_doc_number] => 05796653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Circuit for the selection of redundant memory elements and flash EEPROM memory comprising said circuit' [patent_app_type] => 1 [patent_app_number] => 8/394314 [patent_app_country] => US [patent_app_date] => 1995-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4676 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796653.pdf [firstpage_image] =>[orig_patent_app_number] => 394314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/394314
Circuit for the selection of redundant memory elements and flash EEPROM memory comprising said circuit Feb 21, 1995 Issued
Array ( [id] => 3608668 [patent_doc_number] => 05559744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Semiconductor integrated circuit device having a test mode setting circuit' [patent_app_type] => 1 [patent_app_number] => 8/389165 [patent_app_country] => US [patent_app_date] => 1995-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7131 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559744.pdf [firstpage_image] =>[orig_patent_app_number] => 389165 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/389165
Semiconductor integrated circuit device having a test mode setting circuit Feb 14, 1995 Issued
Array ( [id] => 3736461 [patent_doc_number] => 05652724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Burst EDO memory device having pipelined output buffer' [patent_app_type] => 1 [patent_app_number] => 8/386563 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8279 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652724.pdf [firstpage_image] =>[orig_patent_app_number] => 386563 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386563
Burst EDO memory device having pipelined output buffer Feb 9, 1995 Issued
Array ( [id] => 3602817 [patent_doc_number] => 05521864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Non-volatile semiconductor memory device allowing fast verifying operation' [patent_app_type] => 1 [patent_app_number] => 8/385866 [patent_app_country] => US [patent_app_date] => 1995-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 7687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521864.pdf [firstpage_image] =>[orig_patent_app_number] => 385866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/385866
Non-volatile semiconductor memory device allowing fast verifying operation Feb 8, 1995 Issued
08/385470 SEMICONDUCTOR MEMORY DEVICE HAVING A MEMORY CELL CAPACITOR AND A FABRICATION PROCESS THEREOF Feb 7, 1995 Abandoned
Array ( [id] => 3566305 [patent_doc_number] => 05544125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Semiconductor integrated circuit having logic gates' [patent_app_type] => 1 [patent_app_number] => 8/383866 [patent_app_country] => US [patent_app_date] => 1995-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 11207 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544125.pdf [firstpage_image] =>[orig_patent_app_number] => 383866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/383866
Semiconductor integrated circuit having logic gates Feb 5, 1995 Issued
Array ( [id] => 3623507 [patent_doc_number] => 05535171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Data output buffer of a semiconducter memory device' [patent_app_type] => 1 [patent_app_number] => 8/383767 [patent_app_country] => US [patent_app_date] => 1995-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2030 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535171.pdf [firstpage_image] =>[orig_patent_app_number] => 383767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/383767
Data output buffer of a semiconducter memory device Feb 2, 1995 Issued
Array ( [id] => 3507536 [patent_doc_number] => 05532957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Field reconfigurable logic/memory array' [patent_app_type] => 1 [patent_app_number] => 8/381180 [patent_app_country] => US [patent_app_date] => 1995-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1673 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532957.pdf [firstpage_image] =>[orig_patent_app_number] => 381180 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/381180
Field reconfigurable logic/memory array Jan 30, 1995 Issued
Array ( [id] => 4384237 [patent_doc_number] => 06288941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks' [patent_app_type] => 1 [patent_app_number] => 8/379020 [patent_app_country] => US [patent_app_date] => 1995-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 12594 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288941.pdf [firstpage_image] =>[orig_patent_app_number] => 379020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/379020
Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks Jan 26, 1995 Issued
Array ( [id] => 3582561 [patent_doc_number] => 05539698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Redundancy circuit device' [patent_app_type] => 1 [patent_app_number] => 8/378268 [patent_app_country] => US [patent_app_date] => 1995-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 7 [patent_no_of_words] => 7091 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539698.pdf [firstpage_image] =>[orig_patent_app_number] => 378268 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/378268
Redundancy circuit device Jan 25, 1995 Issued
Array ( [id] => 3699199 [patent_doc_number] => 05604708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Fail-safe system for preserving a backup battery' [patent_app_type] => 1 [patent_app_number] => 8/378169 [patent_app_country] => US [patent_app_date] => 1995-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3551 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604708.pdf [firstpage_image] =>[orig_patent_app_number] => 378169 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/378169
Fail-safe system for preserving a backup battery Jan 24, 1995 Issued
Array ( [id] => 3608818 [patent_doc_number] => 05559753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Apparatus and method for preventing bus contention during power-up in a computer system with two or more DRAM banks' [patent_app_type] => 1 [patent_app_number] => 8/378164 [patent_app_country] => US [patent_app_date] => 1995-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3437 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559753.pdf [firstpage_image] =>[orig_patent_app_number] => 378164 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/378164
Apparatus and method for preventing bus contention during power-up in a computer system with two or more DRAM banks Jan 24, 1995 Issued
Array ( [id] => 3576999 [patent_doc_number] => 05485425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Semiconductor memory device having redundant column and operation method thereof' [patent_app_type] => 1 [patent_app_number] => 8/375727 [patent_app_country] => US [patent_app_date] => 1995-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7956 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485425.pdf [firstpage_image] =>[orig_patent_app_number] => 375727 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375727
Semiconductor memory device having redundant column and operation method thereof Jan 19, 1995 Issued
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