Amir Zarabian

Array ( [id] => 3515396 [patent_doc_number] => 05515310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Six transistor dynamic content addressable memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/357848 [patent_app_country] => US [patent_app_date] => 1994-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3636 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515310.pdf [firstpage_image] =>[orig_patent_app_number] => 357848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3678463 [patent_doc_number] => 05600598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Memory cell and wordline driver for embedded DRAM in ASIC process' [patent_app_type] => 1 [patent_app_number] => 8/355956 [patent_app_country] => US [patent_app_date] => 1994-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3712 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600598.pdf [firstpage_image] =>[orig_patent_app_number] => 355956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3596595 [patent_doc_number] => 05553021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Semiconductor integrated circuit device including a voltage generator for providing desired interval internal voltages' [patent_app_type] => 1 [patent_app_number] => 8/354623 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 10162 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553021.pdf [firstpage_image] =>[orig_patent_app_number] => 354623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3613095 [patent_doc_number] => 05579275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Video memory system' [patent_app_type] => 1 [patent_app_number] => 8/353675 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 5377 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579275.pdf [firstpage_image] =>[orig_patent_app_number] => 353675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3678394 [patent_doc_number] => 05600593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Apparatus and method for reducing erased threshold voltage distribution in flash memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/349812 [patent_app_country] => US [patent_app_date] => 1994-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6492 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600593.pdf [firstpage_image] =>[orig_patent_app_number] => 349812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3602908 [patent_doc_number] => 05521870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Semiconductor memory device having a coincidence detection circuit and its test method' [patent_app_type] => 1 [patent_app_number] => 8/354086 [patent_app_country] => US [patent_app_date] => 1994-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3595 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521870.pdf [firstpage_image] =>[orig_patent_app_number] => 354086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3120596 [patent_doc_number] => 05465237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'RAS encoded generator for a memory bank' [patent_app_type] => 1 [patent_app_number] => 8/347967 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3463 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465237.pdf [firstpage_image] =>[orig_patent_app_number] => 347967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3471947 [patent_doc_number] => 05469397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Semiconductor memory device with a reference potential generator' [patent_app_type] => 1 [patent_app_number] => 8/337209 [patent_app_country] => US [patent_app_date] => 1994-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2581 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469397.pdf [firstpage_image] =>[orig_patent_app_number] => 337209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3664369 [patent_doc_number] => 05623436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method and apparatus for adjustment and control of an iterative method of recording analog signals with on-chip trimming techniques' [patent_app_type] => 1 [patent_app_number] => 8/334589 [patent_app_country] => US [patent_app_date] => 1994-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8308 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623436.pdf [firstpage_image] =>[orig_patent_app_number] => 334589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3600837 [patent_doc_number] => 05488587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Non-volatile dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/325957 [patent_app_country] => US [patent_app_date] => 1994-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 20159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488587.pdf [firstpage_image] =>[orig_patent_app_number] => 325957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3617773 [patent_doc_number] => 05590069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method and apparatus for providing ROM in an integrated circuit having update through single substance layer modification capability' [patent_app_type] => 1 [patent_app_number] => 8/324433 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4727 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590069.pdf [firstpage_image] =>[orig_patent_app_number] => 324433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3526775 [patent_doc_number] => 05576986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Memory device using micro vacuum tube' [patent_app_type] => 1 [patent_app_number] => 8/322491 [patent_app_country] => US [patent_app_date] => 1994-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3799 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/576/05576986.pdf [firstpage_image] =>[orig_patent_app_number] => 322491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3529891 [patent_doc_number] => 05530671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Semiconductor memory device having presetting function of sense amplifier' [patent_app_type] => 1 [patent_app_number] => 8/320457 [patent_app_country] => US [patent_app_date] => 1994-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 7863 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530671.pdf [firstpage_image] =>[orig_patent_app_number] => 320457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873523 [patent_doc_number] => 05796673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Delay locked loop implementation in a synchronous dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/319042 [patent_app_country] => US [patent_app_date] => 1994-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2294 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796673.pdf [firstpage_image] =>[orig_patent_app_number] => 319042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633431 [patent_doc_number] => 05602796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Word line driver in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/318175 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3385 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602796.pdf [firstpage_image] =>[orig_patent_app_number] => 318175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3534682 [patent_doc_number] => 05504711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Bit lines write circuit for SRAM memories' [patent_app_type] => 1 [patent_app_number] => 8/315455 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2109 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504711.pdf [firstpage_image] =>[orig_patent_app_number] => 315455 [rel_patent_id] =>[rel_patent_doc_number] =>)