Search

Amir Zarabian

Supervisory Patent Examiner (ID: 13021, Phone: (571)272-1852 , Office: P/2827 )

Most Active Art Unit
2511
Art Unit(s)
2824, 2602, 2822, 2502, 2511, 2818, 2827
Total Applications
1128
Issued Applications
976
Pending Applications
28
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3624250 [patent_doc_number] => 05511034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Simple temporary information storage circuit controllable with enable/reset signal' [patent_app_type] => 1 [patent_app_number] => 8/282429 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4543 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511034.pdf [firstpage_image] =>[orig_patent_app_number] => 282429 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282429
Simple temporary information storage circuit controllable with enable/reset signal Jul 28, 1994 Issued
08/282045 CONTROL AND MONITORING DEVICE FOR A POWER SWITCH Jul 27, 1994 Abandoned
Array ( [id] => 3515573 [patent_doc_number] => 05515322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Semiconductor memory device equipped with sense amplifiers selectively activated with column address decoded signals' [patent_app_type] => 1 [patent_app_number] => 8/280845 [patent_app_country] => US [patent_app_date] => 1994-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7444 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515322.pdf [firstpage_image] =>[orig_patent_app_number] => 280845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280845
Semiconductor memory device equipped with sense amplifiers selectively activated with column address decoded signals Jul 25, 1994 Issued
Array ( [id] => 3678292 [patent_doc_number] => 05600586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Flat-cell ROM and decoder' [patent_app_type] => 1 [patent_app_number] => 8/279682 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5356 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600586.pdf [firstpage_image] =>[orig_patent_app_number] => 279682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/279682
Flat-cell ROM and decoder Jul 24, 1994 Issued
Array ( [id] => 3623431 [patent_doc_number] => 05535166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Circuit for isolating and driving interconnect lines' [patent_app_type] => 1 [patent_app_number] => 8/280350 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5362 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535166.pdf [firstpage_image] =>[orig_patent_app_number] => 280350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280350
Circuit for isolating and driving interconnect lines Jul 24, 1994 Issued
Array ( [id] => 4131079 [patent_doc_number] => 06072715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Memory circuit and method of construction' [patent_app_type] => 1 [patent_app_number] => 8/279135 [patent_app_country] => US [patent_app_date] => 1994-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2553 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072715.pdf [firstpage_image] =>[orig_patent_app_number] => 279135 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/279135
Memory circuit and method of construction Jul 21, 1994 Issued
Array ( [id] => 3489754 [patent_doc_number] => 05400289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Lockout circuit and method for preventing metastability during the termination of a refresh mode' [patent_app_type] => 1 [patent_app_number] => 8/275693 [patent_app_country] => US [patent_app_date] => 1994-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2920 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/400/05400289.pdf [firstpage_image] =>[orig_patent_app_number] => 275693 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/275693
Lockout circuit and method for preventing metastability during the termination of a refresh mode Jul 14, 1994 Issued
Array ( [id] => 3422206 [patent_doc_number] => 05444664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Flash memory and a microcomputer' [patent_app_type] => 1 [patent_app_number] => 8/274279 [patent_app_country] => US [patent_app_date] => 1994-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 44 [patent_no_of_words] => 18859 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444664.pdf [firstpage_image] =>[orig_patent_app_number] => 274279 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/274279
Flash memory and a microcomputer Jul 12, 1994 Issued
Array ( [id] => 3489282 [patent_doc_number] => 05457650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Apparatus and method for reading multi-level data stored in a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/272682 [patent_app_country] => US [patent_app_date] => 1994-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 55 [patent_no_of_words] => 19680 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457650.pdf [firstpage_image] =>[orig_patent_app_number] => 272682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/272682
Apparatus and method for reading multi-level data stored in a semiconductor memory Jul 7, 1994 Issued
Array ( [id] => 3482560 [patent_doc_number] => 05477502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Semiconductor RAM device with a single write signal line for one column in memory cell array and for one port' [patent_app_type] => 1 [patent_app_number] => 8/272033 [patent_app_country] => US [patent_app_date] => 1994-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3930 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477502.pdf [firstpage_image] =>[orig_patent_app_number] => 272033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/272033
Semiconductor RAM device with a single write signal line for one column in memory cell array and for one port Jul 7, 1994 Issued
Array ( [id] => 3419085 [patent_doc_number] => 05461590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Low power VCC and temperature independent oscillator' [patent_app_type] => 1 [patent_app_number] => 8/271719 [patent_app_country] => US [patent_app_date] => 1994-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4963 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461590.pdf [firstpage_image] =>[orig_patent_app_number] => 271719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/271719
Low power VCC and temperature independent oscillator Jul 6, 1994 Issued
Array ( [id] => 3424960 [patent_doc_number] => 05453954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Semiconductor integrated circuit device with built-in regulating system for determining margins of main circuits' [patent_app_type] => 1 [patent_app_number] => 8/270834 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5066 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453954.pdf [firstpage_image] =>[orig_patent_app_number] => 270834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270834
Semiconductor integrated circuit device with built-in regulating system for determining margins of main circuits Jul 4, 1994 Issued
Array ( [id] => 3489324 [patent_doc_number] => 05457653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Technique to prevent deprogramming a floating gate transistor used to directly switch a large electrical signal' [patent_app_type] => 1 [patent_app_number] => 8/270869 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2817 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457653.pdf [firstpage_image] =>[orig_patent_app_number] => 270869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270869
Technique to prevent deprogramming a floating gate transistor used to directly switch a large electrical signal Jul 4, 1994 Issued
Array ( [id] => 3546736 [patent_doc_number] => 05495437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Non-volatile RAM transferring data between ferro-electric capacitors and a memory cell' [patent_app_type] => 1 [patent_app_number] => 8/270274 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3053 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495437.pdf [firstpage_image] =>[orig_patent_app_number] => 270274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270274
Non-volatile RAM transferring data between ferro-electric capacitors and a memory cell Jul 4, 1994 Issued
Array ( [id] => 3437190 [patent_doc_number] => 05455799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Circuit which provides power on reset disable during a test mode' [patent_app_type] => 1 [patent_app_number] => 8/267666 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455799.pdf [firstpage_image] =>[orig_patent_app_number] => 267666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/267666
Circuit which provides power on reset disable during a test mode Jun 28, 1994 Issued
Array ( [id] => 3541252 [patent_doc_number] => 05583816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Long write test' [patent_app_type] => 1 [patent_app_number] => 8/267667 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3456 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583816.pdf [firstpage_image] =>[orig_patent_app_number] => 267667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/267667
Long write test Jun 28, 1994 Issued
Array ( [id] => 3489432 [patent_doc_number] => 05457661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Semiconductor memory device having a delay circuit for controlling access time' [patent_app_type] => 1 [patent_app_number] => 8/264775 [patent_app_country] => US [patent_app_date] => 1994-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4208 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457661.pdf [firstpage_image] =>[orig_patent_app_number] => 264775 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/264775
Semiconductor memory device having a delay circuit for controlling access time Jun 22, 1994 Issued
Array ( [id] => 3544893 [patent_doc_number] => 05557582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Semiconductor memory device inhibiting invalid data from being output' [patent_app_type] => 1 [patent_app_number] => 8/264076 [patent_app_country] => US [patent_app_date] => 1994-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5545 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557582.pdf [firstpage_image] =>[orig_patent_app_number] => 264076 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/264076
Semiconductor memory device inhibiting invalid data from being output Jun 21, 1994 Issued
Array ( [id] => 3435513 [patent_doc_number] => 05404328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Memory cell having floating gate and semiconductor memory using the same' [patent_app_type] => 1 [patent_app_number] => 8/262352 [patent_app_country] => US [patent_app_date] => 1994-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5650 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404328.pdf [firstpage_image] =>[orig_patent_app_number] => 262352 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/262352
Memory cell having floating gate and semiconductor memory using the same Jun 19, 1994 Issued
Array ( [id] => 3572772 [patent_doc_number] => 05526305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Two-transistor dynamic random-access memory cell' [patent_app_type] => 1 [patent_app_number] => 8/265463 [patent_app_country] => US [patent_app_date] => 1994-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2636 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526305.pdf [firstpage_image] =>[orig_patent_app_number] => 265463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/265463
Two-transistor dynamic random-access memory cell Jun 16, 1994 Issued
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