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Amir Zarabian

Supervisory Patent Examiner (ID: 13021, Phone: (571)272-1852 , Office: P/2827 )

Most Active Art Unit
2511
Art Unit(s)
2824, 2602, 2822, 2502, 2511, 2818, 2827
Total Applications
1128
Issued Applications
976
Pending Applications
28
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
08/254028 PIPELINED READ ARCHITECTURE FOR MEMORY Jun 2, 1994 Abandoned
08/254083 FABRICATION PROCESS FOR A 1-TRANSISTOR EEPROM MEMORY DEVICE CAPABLE OF LOW-VOLTAGE OPERATION Jun 2, 1994 Abandoned
08/252686 DYNAMIC SINGLE BIT PER CELL TO MULTIPLE BIT PER CELL MEMORY Jun 1, 1994 Abandoned
Array ( [id] => 3576953 [patent_doc_number] => 05485422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Drain bias multiplexing for multiple bit flash cell' [patent_app_type] => 1 [patent_app_number] => 8/252684 [patent_app_country] => US [patent_app_date] => 1994-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6890 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485422.pdf [firstpage_image] =>[orig_patent_app_number] => 252684 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252684
Drain bias multiplexing for multiple bit flash cell Jun 1, 1994 Issued
Array ( [id] => 3582444 [patent_doc_number] => 05539690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Write verify schemes for flash memory with multilevel cells' [patent_app_type] => 1 [patent_app_number] => 8/252747 [patent_app_country] => US [patent_app_date] => 1994-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8997 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539690.pdf [firstpage_image] =>[orig_patent_app_number] => 252747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252747
Write verify schemes for flash memory with multilevel cells Jun 1, 1994 Issued
Array ( [id] => 3523410 [patent_doc_number] => 05513140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Data output buffer' [patent_app_type] => 1 [patent_app_number] => 8/252421 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513140.pdf [firstpage_image] =>[orig_patent_app_number] => 252421 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252421
Data output buffer May 31, 1994 Issued
Array ( [id] => 3546854 [patent_doc_number] => 05495445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Redundancy scheme for memory circuits' [patent_app_type] => 1 [patent_app_number] => 8/252284 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3630 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495445.pdf [firstpage_image] =>[orig_patent_app_number] => 252284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252284
Redundancy scheme for memory circuits May 30, 1994 Issued
Array ( [id] => 4393971 [patent_doc_number] => 06295241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Dynamic random access memory device' [patent_app_type] => 1 [patent_app_number] => 8/251649 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 58 [patent_no_of_words] => 14083 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295241.pdf [firstpage_image] =>[orig_patent_app_number] => 251649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251649
Dynamic random access memory device May 30, 1994 Issued
Array ( [id] => 3455593 [patent_doc_number] => 05420820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'RAS input disable circuit' [patent_app_type] => 1 [patent_app_number] => 8/251824 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2320 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420820.pdf [firstpage_image] =>[orig_patent_app_number] => 251824 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251824
RAS input disable circuit May 30, 1994 Issued
Array ( [id] => 3451597 [patent_doc_number] => 05398210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Semiconductor memory device having memory cells reorganizable into memory cell blocks different in size' [patent_app_type] => 1 [patent_app_number] => 8/250688 [patent_app_country] => US [patent_app_date] => 1994-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4427 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398210.pdf [firstpage_image] =>[orig_patent_app_number] => 250688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/250688
Semiconductor memory device having memory cells reorganizable into memory cell blocks different in size May 26, 1994 Issued
08/250746 SEMICONDUCTOR-INTEGRATED-CIRCUIT SRAM-CELL ARRAY WITH SINGLE-ENDED CURRENT-SENSING May 26, 1994 Abandoned
Array ( [id] => 3774857 [patent_doc_number] => 05844842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/249899 [patent_app_country] => US [patent_app_date] => 1994-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 78 [patent_no_of_words] => 39659 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 573 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844842.pdf [firstpage_image] =>[orig_patent_app_number] => 249899 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/249899
Nonvolatile semiconductor memory device May 25, 1994 Issued
08/249801 FLAT-CELL ROM AND DECODER May 25, 1994 Abandoned
Array ( [id] => 3462947 [patent_doc_number] => 05379249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'UPROM programming protect circuit' [patent_app_type] => 1 [patent_app_number] => 8/249055 [patent_app_country] => US [patent_app_date] => 1994-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3473 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379249.pdf [firstpage_image] =>[orig_patent_app_number] => 249055 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/249055
UPROM programming protect circuit May 24, 1994 Issued
Array ( [id] => 3577043 [patent_doc_number] => 05485428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Memory device with page select capability' [patent_app_type] => 1 [patent_app_number] => 8/248520 [patent_app_country] => US [patent_app_date] => 1994-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4117 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485428.pdf [firstpage_image] =>[orig_patent_app_number] => 248520 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/248520
Memory device with page select capability May 23, 1994 Issued
Array ( [id] => 3576902 [patent_doc_number] => 05485419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Memory device column address selection lead layout' [patent_app_type] => 1 [patent_app_number] => 8/247914 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2737 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485419.pdf [firstpage_image] =>[orig_patent_app_number] => 247914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247914
Memory device column address selection lead layout May 22, 1994 Issued
Array ( [id] => 3624177 [patent_doc_number] => 05511029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Test circuit in clock synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/246582 [patent_app_country] => US [patent_app_date] => 1994-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 39 [patent_no_of_words] => 17792 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511029.pdf [firstpage_image] =>[orig_patent_app_number] => 246582 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/246582
Test circuit in clock synchronous semiconductor memory device May 18, 1994 Issued
Array ( [id] => 3437250 [patent_doc_number] => 05455803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Semiconductor device which operates at a frequency controlled by an external clock signal' [patent_app_type] => 1 [patent_app_number] => 8/231677 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 35 [patent_no_of_words] => 3834 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455803.pdf [firstpage_image] =>[orig_patent_app_number] => 231677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231677
Semiconductor device which operates at a frequency controlled by an external clock signal Apr 24, 1994 Issued
Array ( [id] => 4131248 [patent_doc_number] => 06062698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'System for creating video generated decorative images' [patent_app_type] => 1 [patent_app_number] => 8/229619 [patent_app_country] => US [patent_app_date] => 1994-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/062/06062698.pdf [firstpage_image] =>[orig_patent_app_number] => 229619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229619
System for creating video generated decorative images Apr 18, 1994 Issued
Array ( [id] => 3525503 [patent_doc_number] => 05487050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Decoding circuit and method for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/229082 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3360 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/487/05487050.pdf [firstpage_image] =>[orig_patent_app_number] => 229082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229082
Decoding circuit and method for a semiconductor memory device Apr 17, 1994 Issued
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