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Amir Zarabian

Supervisory Patent Examiner (ID: 13021, Phone: (571)272-1852 , Office: P/2827 )

Most Active Art Unit
2511
Art Unit(s)
2824, 2602, 2822, 2502, 2511, 2818, 2827
Total Applications
1128
Issued Applications
976
Pending Applications
28
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3462931 [patent_doc_number] => 05379248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/181524 [patent_app_country] => US [patent_app_date] => 1994-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 49 [patent_no_of_words] => 9357 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379248.pdf [firstpage_image] =>[orig_patent_app_number] => 181524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/181524
Semiconductor memory device Jan 12, 1994 Issued
Array ( [id] => 4197040 [patent_doc_number] => 06160738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Nonvolatile semiconductor memory system' [patent_app_type] => 1 [patent_app_number] => 8/181404 [patent_app_country] => US [patent_app_date] => 1994-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6769 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160738.pdf [firstpage_image] =>[orig_patent_app_number] => 181404 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/181404
Nonvolatile semiconductor memory system Jan 12, 1994 Issued
Array ( [id] => 3435541 [patent_doc_number] => 05404330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Word line boosting circuit and control circuit therefor in a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/161851 [patent_app_country] => US [patent_app_date] => 1993-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3785 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404330.pdf [firstpage_image] =>[orig_patent_app_number] => 161851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/161851
Word line boosting circuit and control circuit therefor in a semiconductor integrated circuit Dec 5, 1993 Issued
08/160840 DYNAMIC RANDOM ACCESS MEMORY Dec 2, 1993 Abandoned
Array ( [id] => 3114364 [patent_doc_number] => 05448527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Decoder and driver for use in a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/149936 [patent_app_country] => US [patent_app_date] => 1993-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 6311 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448527.pdf [firstpage_image] =>[orig_patent_app_number] => 149936 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/149936
Decoder and driver for use in a semiconductor memory Nov 9, 1993 Issued
Array ( [id] => 3103961 [patent_doc_number] => 05369615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-29 [patent_title] => 'Method for optimum erasing of EEPROM' [patent_app_type] => 1 [patent_app_number] => 8/149602 [patent_app_country] => US [patent_app_date] => 1993-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 11476 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/369/05369615.pdf [firstpage_image] =>[orig_patent_app_number] => 149602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/149602
Method for optimum erasing of EEPROM Nov 7, 1993 Issued
08/147555 STATIC RAM Nov 4, 1993 Abandoned
08/141101 SEMICONDUCTOR MEMORY DEVICE WITH FUNCTION OF PREVENTING LOSS OF INFORMATION DUE TO LEAK OF CHARGES OF DISTURBING Oct 25, 1993 Abandoned
Array ( [id] => 3491556 [patent_doc_number] => 05406523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'High voltage boosted word line supply charge pump and regulator for DRAM' [patent_app_type] => 1 [patent_app_number] => 8/134621 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3699 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406523.pdf [firstpage_image] =>[orig_patent_app_number] => 134621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/134621
High voltage boosted word line supply charge pump and regulator for DRAM Oct 11, 1993 Issued
Array ( [id] => 3464133 [patent_doc_number] => 05452253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Burn-in test circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/125574 [patent_app_country] => US [patent_app_date] => 1993-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3636 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452253.pdf [firstpage_image] =>[orig_patent_app_number] => 125574 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/125574
Burn-in test circuit for semiconductor memory device Sep 22, 1993 Issued
08/121504 SYNCHRONOUS BURST-ACCESS MEMORY Sep 14, 1993 Issued
Array ( [id] => 3470941 [patent_doc_number] => 05392249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Random access memory' [patent_app_type] => 1 [patent_app_number] => 8/120739 [patent_app_country] => US [patent_app_date] => 1993-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 12876 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392249.pdf [firstpage_image] =>[orig_patent_app_number] => 120739 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/120739
Random access memory Sep 13, 1993 Issued
08/119870 METHOD AND APPARATUS FOR CONTROLLING THE OUTPUT VOLTAGE PROVIDED BY A CHARGE PUMP CIRCUIT Sep 9, 1993 Abandoned
Array ( [id] => 3464016 [patent_doc_number] => 05452245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Memory efficient gate array cell' [patent_app_type] => 1 [patent_app_number] => 8/124651 [patent_app_country] => US [patent_app_date] => 1993-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2514 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452245.pdf [firstpage_image] =>[orig_patent_app_number] => 124651 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/124651
Memory efficient gate array cell Sep 6, 1993 Issued
Array ( [id] => 3451497 [patent_doc_number] => 05398203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Memory programming load-line circuit with dual slope I-V curve' [patent_app_type] => 1 [patent_app_number] => 8/115217 [patent_app_country] => US [patent_app_date] => 1993-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5417 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398203.pdf [firstpage_image] =>[orig_patent_app_number] => 115217 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/115217
Memory programming load-line circuit with dual slope I-V curve Aug 31, 1993 Issued
Array ( [id] => 3466684 [patent_doc_number] => 05402379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Precharge device for an integrated circuit internal bus' [patent_app_type] => 1 [patent_app_number] => 8/114749 [patent_app_country] => US [patent_app_date] => 1993-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3678 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402379.pdf [firstpage_image] =>[orig_patent_app_number] => 114749 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/114749
Precharge device for an integrated circuit internal bus Aug 30, 1993 Issued
Array ( [id] => 3458035 [patent_doc_number] => 05386380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Bypass scheme for ROM IC' [patent_app_type] => 1 [patent_app_number] => 8/095261 [patent_app_country] => US [patent_app_date] => 1993-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1440 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386380.pdf [firstpage_image] =>[orig_patent_app_number] => 095261 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/095261
Bypass scheme for ROM IC Jul 20, 1993 Issued
Array ( [id] => 3489614 [patent_doc_number] => 05400280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Nonvolatile memory and a method of writing data thereto' [patent_app_type] => 1 [patent_app_number] => 8/089330 [patent_app_country] => US [patent_app_date] => 1993-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2860 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/400/05400280.pdf [firstpage_image] =>[orig_patent_app_number] => 089330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/089330
Nonvolatile memory and a method of writing data thereto Jul 11, 1993 Issued
Array ( [id] => 3498784 [patent_doc_number] => 05471417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Ferroelectric memory cell arrangement' [patent_app_type] => 1 [patent_app_number] => 8/087814 [patent_app_country] => US [patent_app_date] => 1993-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6172 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471417.pdf [firstpage_image] =>[orig_patent_app_number] => 087814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/087814
Ferroelectric memory cell arrangement Jul 8, 1993 Issued
Array ( [id] => 3432863 [patent_doc_number] => 05422842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells' [patent_app_type] => 1 [patent_app_number] => 8/089175 [patent_app_country] => US [patent_app_date] => 1993-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7031 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422842.pdf [firstpage_image] =>[orig_patent_app_number] => 089175 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/089175
Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells Jul 7, 1993 Issued
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