
Amir Zarabian
Supervisory Patent Examiner (ID: 5581, Phone: (571)272-1852 , Office: P/2827 )
| Most Active Art Unit | 2511 |
| Art Unit(s) | 2827, 2818, 2822, 2502, 2511, 2824, 2602 |
| Total Applications | 1135 |
| Issued Applications | 980 |
| Pending Applications | 31 |
| Abandoned Applications | 126 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7635476
[patent_doc_number] => 06381186
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[patent_kind] => B1
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[patent_title] => 'Dynamic random access memory'
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[patent_app_number] => 09/939586
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Array
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Array
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Array
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[patent_title] => 'Method and apparatus for multiple latency synchronous dynamic random access memory'
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Array
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Array
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Array
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Array
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Array
(
[id] => 7077863
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/910745 | Method for checking a semiconductor memory device | Jul 22, 2001 | Issued |
Array
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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