Amir Zarabian

Array ( [id] => 6891644 [patent_doc_number] => 20010017806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Method of repairing defective memory cells of an integrated memory' [patent_app_type] => new [patent_app_number] => 09/793789 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4320 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017806.pdf [firstpage_image] =>[orig_patent_app_number] => 09793789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5872735 [patent_doc_number] => 20020048188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Voltage regulator and data path for a memory device' [patent_app_type] => new [patent_app_number] => 09/792536 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4979 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 36 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048188.pdf [firstpage_image] =>[orig_patent_app_number] => 09792536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1536946 [patent_doc_number] => 06411562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Voltage regulator and data path for a memory device' [patent_app_type] => B1 [patent_app_number] => 09/792537 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4950 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411562.pdf [firstpage_image] =>[orig_patent_app_number] => 09792537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6489216 [patent_doc_number] => 20020024867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Voltage regulator and data path for a memory device' [patent_app_type] => new [patent_app_number] => 09/792553 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4977 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 36 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024867.pdf [firstpage_image] =>[orig_patent_app_number] => 09792553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7013420 [patent_doc_number] => 20010050873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Semiconductor memory with built-in cache' [patent_app_type] => new [patent_app_number] => 09/788262 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 19101 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20010050873.pdf [firstpage_image] =>[orig_patent_app_number] => 09788262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1593556 [patent_doc_number] => 06483750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Flash EEPROM with on-chip erase source voltage generator' [patent_app_type] => B2 [patent_app_number] => 09/768744 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6206 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483750.pdf [firstpage_image] =>[orig_patent_app_number] => 09768744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5984070 [patent_doc_number] => 20020097624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'REFRESH CONTROL CIRCUIT FOR LOW-POWER SRAM APPLICATIONS' [patent_app_type] => new [patent_app_number] => 09/766799 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5334 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20020097624.pdf [firstpage_image] =>[orig_patent_app_number] => 09766799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1488545 [patent_doc_number] => 06366491 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Wide databus architecture' [patent_app_type] => B1 [patent_app_number] => 09/761297 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3073 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366491.pdf [firstpage_image] =>[orig_patent_app_number] => 09761297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7118172 [patent_doc_number] => 20010001598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device' [patent_app_type] => new-utility [patent_app_number] => 09/755170 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 28720 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001598.pdf [firstpage_image] =>[orig_patent_app_number] => 09755170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6877396 [patent_doc_number] => 20010002882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'Semiconductor storage device' [patent_app_type] => new-utility [patent_app_number] => 09/754132 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7771 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002882.pdf [firstpage_image] =>[orig_patent_app_number] => 09754132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1457787 [patent_doc_number] => 06462990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Post erase repair to enhance performance in a flash memory' [patent_app_type] => B1 [patent_app_number] => 09/752197 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4811 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462990.pdf [firstpage_image] =>[orig_patent_app_number] => 09752197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6901155 [patent_doc_number] => 20010022738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Controlling a sense amplifier' [patent_app_type] => new [patent_app_number] => 09/749599 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1491 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022738.pdf [firstpage_image] =>[orig_patent_app_number] => 09749599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6960465 [patent_doc_number] => 20010012229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/748139 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5253 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012229.pdf [firstpage_image] =>[orig_patent_app_number] => 09748139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1480077 [patent_doc_number] => 06344991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/741797 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 87 [patent_no_of_words] => 8990 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344991.pdf [firstpage_image] =>[orig_patent_app_number] => 09741797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7051931 [patent_doc_number] => 20010001263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-17 [patent_title] => 'VPX bank architecture' [patent_app_type] => new-utility [patent_app_number] => 09/745691 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5412 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001263.pdf [firstpage_image] =>[orig_patent_app_number] => 09745691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6875599 [patent_doc_number] => 20010000692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'VPX bank architecture' [patent_app_type] => new-utility [patent_app_number] => 09/745369 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5635 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000692.pdf [firstpage_image] =>[orig_patent_app_number] => 09745369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6947501 [patent_doc_number] => 20010021135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => ' DDR SDRAM for stable read operation' [patent_app_type] => new [patent_app_number] => 09/742815 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2751 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021135.pdf [firstpage_image] =>[orig_patent_app_number] => 09742815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4367008 [patent_doc_number] => 06292409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'System for programmable chip initialization' [patent_app_type] => 1 [patent_app_number] => 9/734999 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1983 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292409.pdf [firstpage_image] =>[orig_patent_app_number] => 734999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1442633 [patent_doc_number] => 06496432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method and apparatus for testing a write function of a dual-port static memory cell' [patent_app_type] => B2 [patent_app_number] => 09/733295 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2699 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496432.pdf [firstpage_image] =>[orig_patent_app_number] => 09733295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5827234 [patent_doc_number] => 20020067654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Synchronous memory modules and memory systems with selectable clock termination' [patent_app_type] => new [patent_app_number] => 09/729013 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2791 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067654.pdf [firstpage_image] =>[orig_patent_app_number] => 09729013 [rel_patent_id] =>[rel_patent_doc_number] =>)