Search

Amjad A. Abraham

Supervisory Patent Examiner (ID: 10466, Phone: (571)270-7058 , Office: P/1663 )

Most Active Art Unit
1744
Art Unit(s)
1744, 1791, 1663
Total Applications
341
Issued Applications
94
Pending Applications
16
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4203572 [patent_doc_number] => 06161163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method of writing, erasing, and controlling memory for memory device' [patent_app_type] => 1 [patent_app_number] => 9/385998 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 9962 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161163.pdf [firstpage_image] =>[orig_patent_app_number] => 385998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385998
Method of writing, erasing, and controlling memory for memory device Aug 29, 1999 Issued
Array ( [id] => 1540043 [patent_doc_number] => 06338114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method, system, and program for using a table to determine an erase operation to perform' [patent_app_type] => B1 [patent_app_number] => 09/377023 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5870 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338114.pdf [firstpage_image] =>[orig_patent_app_number] => 09377023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377023
Method, system, and program for using a table to determine an erase operation to perform Aug 17, 1999 Issued
Array ( [id] => 1587593 [patent_doc_number] => 06425098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Prevention of disk piracy' [patent_app_type] => B1 [patent_app_number] => 09/370813 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8011 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425098.pdf [firstpage_image] =>[orig_patent_app_number] => 09370813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370813
Prevention of disk piracy Aug 8, 1999 Issued
Array ( [id] => 4338107 [patent_doc_number] => 06249911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Optimizing compiler for generating store instructions having memory hierarchy control bits' [patent_app_type] => 1 [patent_app_number] => 9/368756 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3759 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249911.pdf [firstpage_image] =>[orig_patent_app_number] => 368756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368756
Optimizing compiler for generating store instructions having memory hierarchy control bits Aug 4, 1999 Issued
Array ( [id] => 4424745 [patent_doc_number] => 06230242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Store instruction having vertical memory hierarchy control bits' [patent_app_type] => 1 [patent_app_number] => 9/368753 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2589 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230242.pdf [firstpage_image] =>[orig_patent_app_number] => 368753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368753
Store instruction having vertical memory hierarchy control bits Aug 4, 1999 Issued
Array ( [id] => 4337091 [patent_doc_number] => 06249843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Store instruction having horizontal memory hierarchy control bits' [patent_app_type] => 1 [patent_app_number] => 9/368754 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249843.pdf [firstpage_image] =>[orig_patent_app_number] => 368754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368754
Store instruction having horizontal memory hierarchy control bits Aug 4, 1999 Issued
Array ( [id] => 4325383 [patent_doc_number] => 06253286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Apparatus for adjusting a store instruction having memory hierarchy control bits' [patent_app_type] => 1 [patent_app_number] => 9/368755 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4166 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253286.pdf [firstpage_image] =>[orig_patent_app_number] => 368755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368755
Apparatus for adjusting a store instruction having memory hierarchy control bits Aug 4, 1999 Issued
Array ( [id] => 4349673 [patent_doc_number] => 06321305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data' [patent_app_type] => 1 [patent_app_number] => 9/368230 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6747 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321305.pdf [firstpage_image] =>[orig_patent_app_number] => 368230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368230
Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data Aug 3, 1999 Issued
Array ( [id] => 1557264 [patent_doc_number] => 06349367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method and system for communication in which a castout operation is cancelled in response to snoop responses' [patent_app_type] => B1 [patent_app_number] => 09/368228 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6983 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349367.pdf [firstpage_image] =>[orig_patent_app_number] => 09368228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368228
Method and system for communication in which a castout operation is cancelled in response to snoop responses Aug 3, 1999 Issued
Array ( [id] => 4388245 [patent_doc_number] => 06275909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Multiprocessor system bus with system controller explicitly updating snooper cache state information' [patent_app_type] => 1 [patent_app_number] => 9/368226 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275909.pdf [firstpage_image] =>[orig_patent_app_number] => 368226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368226
Multiprocessor system bus with system controller explicitly updating snooper cache state information Aug 3, 1999 Issued
Array ( [id] => 4294600 [patent_doc_number] => 06324617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method and system for communicating tags of data access target and castout victim in a single data transfer' [patent_app_type] => 1 [patent_app_number] => 9/368222 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4057 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324617.pdf [firstpage_image] =>[orig_patent_app_number] => 368222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368222
Method and system for communicating tags of data access target and castout victim in a single data transfer Aug 3, 1999 Issued
Array ( [id] => 4422126 [patent_doc_number] => 06233653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Hierarchical data storage system and data caching method' [patent_app_type] => 1 [patent_app_number] => 9/365711 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3756 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233653.pdf [firstpage_image] =>[orig_patent_app_number] => 365711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365711
Hierarchical data storage system and data caching method Aug 2, 1999 Issued
Array ( [id] => 1572302 [patent_doc_number] => 06378031 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Data processing apparatus and file management method therefor' [patent_app_type] => B1 [patent_app_number] => 09/337951 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15227 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378031.pdf [firstpage_image] =>[orig_patent_app_number] => 09337951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337951
Data processing apparatus and file management method therefor Jun 21, 1999 Issued
Array ( [id] => 1385825 [patent_doc_number] => 06571314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method for changing raid-level in disk array subsystem' [patent_app_type] => B1 [patent_app_number] => 09/254956 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4285 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571314.pdf [firstpage_image] =>[orig_patent_app_number] => 09254956 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/254956
Method for changing raid-level in disk array subsystem Mar 21, 1999 Issued
Array ( [id] => 4310297 [patent_doc_number] => 06212613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Methods and apparatus for reusing addresses in a computer' [patent_app_type] => 1 [patent_app_number] => 9/273925 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212613.pdf [firstpage_image] =>[orig_patent_app_number] => 273925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273925
Methods and apparatus for reusing addresses in a computer Mar 21, 1999 Issued
Array ( [id] => 4423373 [patent_doc_number] => 06311254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Multiple store miss handling in a cache memory memory system' [patent_app_type] => 1 [patent_app_number] => 9/271494 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7795 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311254.pdf [firstpage_image] =>[orig_patent_app_number] => 271494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/271494
Multiple store miss handling in a cache memory memory system Mar 17, 1999 Issued
Array ( [id] => 4381309 [patent_doc_number] => 06256714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Computer system with efficient memory usage for managing multiple application programs' [patent_app_type] => 1 [patent_app_number] => 9/270932 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3527 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256714.pdf [firstpage_image] =>[orig_patent_app_number] => 270932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270932
Computer system with efficient memory usage for managing multiple application programs Mar 15, 1999 Issued
Array ( [id] => 1584711 [patent_doc_number] => 06449679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-10 [patent_title] => 'RAM controller interface device for RAM compatibility (memory translator hub)' [patent_app_type] => B2 [patent_app_number] => 09/258466 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3804 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449679.pdf [firstpage_image] =>[orig_patent_app_number] => 09258466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258466
RAM controller interface device for RAM compatibility (memory translator hub) Feb 25, 1999 Issued
Array ( [id] => 4304753 [patent_doc_number] => 06269428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system' [patent_app_type] => 1 [patent_app_number] => 9/259367 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3739 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269428.pdf [firstpage_image] =>[orig_patent_app_number] => 259367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259367
Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system Feb 25, 1999 Issued
Array ( [id] => 4426608 [patent_doc_number] => 06178479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Cycle-skipping DRAM for power saving' [patent_app_type] => 1 [patent_app_number] => 9/255040 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178479.pdf [firstpage_image] =>[orig_patent_app_number] => 255040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255040
Cycle-skipping DRAM for power saving Feb 21, 1999 Issued
Menu