Search

Amjad A. Abraham

Supervisory Patent Examiner (ID: 10466, Phone: (571)270-7058 , Office: P/1663 )

Most Active Art Unit
1744
Art Unit(s)
1744, 1791, 1663
Total Applications
341
Issued Applications
94
Pending Applications
16
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4121896 [patent_doc_number] => 06052756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Memory page management' [patent_app_type] => 1 [patent_app_number] => 9/012242 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7373 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052756.pdf [firstpage_image] =>[orig_patent_app_number] => 012242 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012242
Memory page management Jan 22, 1998 Issued
Array ( [id] => 4176760 [patent_doc_number] => 06157990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Independent chip select for SRAM and DRAM in a multi-port RAM' [patent_app_type] => 1 [patent_app_number] => 9/012460 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4496 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157990.pdf [firstpage_image] =>[orig_patent_app_number] => 012460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012460
Independent chip select for SRAM and DRAM in a multi-port RAM Jan 22, 1998 Issued
Array ( [id] => 4147699 [patent_doc_number] => 06128716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Memory controller with continuous page mode and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/010976 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2592 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128716.pdf [firstpage_image] =>[orig_patent_app_number] => 010976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010976
Memory controller with continuous page mode and method therefor Jan 22, 1998 Issued
Array ( [id] => 4171965 [patent_doc_number] => 06125459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Information storing method, information storing unit, and disk drive' [patent_app_type] => 1 [patent_app_number] => 9/012360 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3374 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125459.pdf [firstpage_image] =>[orig_patent_app_number] => 012360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012360
Information storing method, information storing unit, and disk drive Jan 22, 1998 Issued
Array ( [id] => 4199142 [patent_doc_number] => 06038646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method and apparatus for enforcing ordered execution of reads and writes across a memory interface' [patent_app_type] => 1 [patent_app_number] => 9/012882 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6397 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038646.pdf [firstpage_image] =>[orig_patent_app_number] => 012882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012882
Method and apparatus for enforcing ordered execution of reads and writes across a memory interface Jan 22, 1998 Issued
Array ( [id] => 4171438 [patent_doc_number] => 06125424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of writing, erasing, and controlling memory and memory device having erasing and moving components' [patent_app_type] => 1 [patent_app_number] => 9/010795 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 90 [patent_no_of_words] => 16211 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125424.pdf [firstpage_image] =>[orig_patent_app_number] => 010795 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010795
Method of writing, erasing, and controlling memory and memory device having erasing and moving components Jan 21, 1998 Issued
Array ( [id] => 4223797 [patent_doc_number] => 06078988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'High speed data recording and reproducing apparatus and method that mutually monitors the using ratios of buffer memories to thereby control the reading or writing operation' [patent_app_type] => 1 [patent_app_number] => 9/012181 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6833 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078988.pdf [firstpage_image] =>[orig_patent_app_number] => 012181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012181
High speed data recording and reproducing apparatus and method that mutually monitors the using ratios of buffer memories to thereby control the reading or writing operation Jan 21, 1998 Issued
Array ( [id] => 4203968 [patent_doc_number] => 06151658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Write-buffer FIFO architecture with random access snooping capability' [patent_app_type] => 1 [patent_app_number] => 9/008394 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151658.pdf [firstpage_image] =>[orig_patent_app_number] => 008394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008394
Write-buffer FIFO architecture with random access snooping capability Jan 15, 1998 Issued
Array ( [id] => 4152767 [patent_doc_number] => 06148388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Extended page mode with memory address translation using a linear shift register' [patent_app_type] => 1 [patent_app_number] => 9/007621 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5701 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148388.pdf [firstpage_image] =>[orig_patent_app_number] => 007621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007621
Extended page mode with memory address translation using a linear shift register Jan 14, 1998 Issued
Array ( [id] => 4200144 [patent_doc_number] => 06021482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Extended page mode with a skipped logical addressing for an embedded longitudinal redundancy check scheme' [patent_app_type] => 1 [patent_app_number] => 9/007618 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7345 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021482.pdf [firstpage_image] =>[orig_patent_app_number] => 007618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007618
Extended page mode with a skipped logical addressing for an embedded longitudinal redundancy check scheme Jan 14, 1998 Issued
Array ( [id] => 4260207 [patent_doc_number] => 06167487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Multi-port RAM having functionally identical ports' [patent_app_type] => 1 [patent_app_number] => 9/006190 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4939 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167487.pdf [firstpage_image] =>[orig_patent_app_number] => 006190 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006190
Multi-port RAM having functionally identical ports Jan 12, 1998 Issued
Array ( [id] => 4123949 [patent_doc_number] => 06101579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Multi-port memory device having masking registers' [patent_app_type] => 1 [patent_app_number] => 9/006191 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101579.pdf [firstpage_image] =>[orig_patent_app_number] => 006191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006191
Multi-port memory device having masking registers Jan 12, 1998 Issued
Array ( [id] => 4040654 [patent_doc_number] => 05926829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Hybrid NUMA COMA caching system and methods for selecting between the caching modes' [patent_app_type] => 1 [patent_app_number] => 9/005058 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926829.pdf [firstpage_image] =>[orig_patent_app_number] => 005058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005058
Hybrid NUMA COMA caching system and methods for selecting between the caching modes Jan 8, 1998 Issued
Array ( [id] => 4317818 [patent_doc_number] => 06182189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method and apparatus for placing a memory in a read-while-write mode' [patent_app_type] => 1 [patent_app_number] => 9/002691 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5283 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182189.pdf [firstpage_image] =>[orig_patent_app_number] => 002691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002691
Method and apparatus for placing a memory in a read-while-write mode Jan 4, 1998 Issued
Array ( [id] => 4252532 [patent_doc_number] => 06076148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Mass storage subsystem and backup arrangement for digital data processing system which permits information to be backed up while host computer(s) continue(s) operating in connection with information stored on mass storage subsystem' [patent_app_type] => 1 [patent_app_number] => 8/998463 [patent_app_country] => US [patent_app_date] => 1997-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10696 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076148.pdf [firstpage_image] =>[orig_patent_app_number] => 998463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998463
Mass storage subsystem and backup arrangement for digital data processing system which permits information to be backed up while host computer(s) continue(s) operating in connection with information stored on mass storage subsystem Dec 25, 1997 Issued
Array ( [id] => 4121924 [patent_doc_number] => 06052758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Interface error detection and isolation in a direct access storage device DASD system' [patent_app_type] => 1 [patent_app_number] => 8/996055 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4432 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052758.pdf [firstpage_image] =>[orig_patent_app_number] => 996055 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996055
Interface error detection and isolation in a direct access storage device DASD system Dec 21, 1997 Issued
Array ( [id] => 1395335 [patent_doc_number] => 06567889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Apparatus and method to provide virtual solid state disk in cache memory in a storage controller' [patent_app_type] => B1 [patent_app_number] => 08/994250 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6801 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567889.pdf [firstpage_image] =>[orig_patent_app_number] => 08994250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994250
Apparatus and method to provide virtual solid state disk in cache memory in a storage controller Dec 18, 1997 Issued
Array ( [id] => 4122001 [patent_doc_number] => 06052763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Multiprocessor system memory unit with split bus and method for controlling access to the memory unit' [patent_app_type] => 1 [patent_app_number] => 8/992097 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6940 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052763.pdf [firstpage_image] =>[orig_patent_app_number] => 992097 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992097
Multiprocessor system memory unit with split bus and method for controlling access to the memory unit Dec 16, 1997 Issued
Array ( [id] => 3932876 [patent_doc_number] => 06003118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method and apparatus for synchronizing clock distribution of a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/991768 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4496 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003118.pdf [firstpage_image] =>[orig_patent_app_number] => 991768 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991768
Method and apparatus for synchronizing clock distribution of a data processing system Dec 15, 1997 Issued
Array ( [id] => 4138761 [patent_doc_number] => 06073212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags' [patent_app_type] => 1 [patent_app_number] => 8/940217 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073212.pdf [firstpage_image] =>[orig_patent_app_number] => 940217 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940217
Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags Sep 29, 1997 Issued
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