Search

Amy Regina Weisberg

Examiner (ID: 13118, Phone: (571)270-5500 , Office: P/3731 )

Most Active Art Unit
3649
Art Unit(s)
3612, 3734, 3771, 3649, 3731
Total Applications
622
Issued Applications
338
Pending Applications
15
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12760129 [patent_doc_number] => 20180145211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => OPTOELECTRONIC ARRANGEMENT AND DEPTH MEASURING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/577626 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15577626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/577626
OPTOELECTRONIC ARRANGEMENT AND DEPTH MEASURING SYSTEM May 26, 2016 Abandoned
Array ( [id] => 11645082 [patent_doc_number] => 09666473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/160278 [patent_app_country] => US [patent_app_date] => 2016-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3138 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15160278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/160278
Manufacturing method of semiconductor device May 19, 2016 Issued
Array ( [id] => 11313627 [patent_doc_number] => 20160349736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'METROLOGY SAMPLING METHOD WITH SAMPLING RATE DECISION SCHEME AND COMPUTER PROGRAM PRODUCT THEREOF' [patent_app_type] => utility [patent_app_number] => 15/158604 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15158604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/158604
Metrology sampling method with sampling rate decision scheme and computer program product thereof May 18, 2016 Issued
Array ( [id] => 12760108 [patent_doc_number] => 20180145204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => DEVICE FOR DIRECT X-RAY DETECTION [patent_app_type] => utility [patent_app_number] => 15/575158 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15575158 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/575158
Device for direct X-ray detection May 17, 2016 Issued
Array ( [id] => 15857187 [patent_doc_number] => 10643890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Ultrathin multilayer metal alloy liner for nano Cu interconnects [patent_app_type] => utility [patent_app_number] => 15/151230 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 7733 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151230
Ultrathin multilayer metal alloy liner for nano Cu interconnects May 9, 2016 Issued
Array ( [id] => 11079252 [patent_doc_number] => 20160276216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 15/151260 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8293 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151260 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151260
ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS May 9, 2016 Abandoned
Array ( [id] => 17224657 [patent_doc_number] => 11177167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Ultrathin multilayer metal alloy liner for nano Cu interconnects [patent_app_type] => utility [patent_app_number] => 15/150961 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 8161 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15150961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/150961
Ultrathin multilayer metal alloy liner for nano Cu interconnects May 9, 2016 Issued
Array ( [id] => 11898306 [patent_doc_number] => 09768247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Semiconductor device having improved superjunction trench structure and method of manufacture' [patent_app_type] => utility [patent_app_number] => 15/148170 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148170 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148170
Semiconductor device having improved superjunction trench structure and method of manufacture May 5, 2016 Issued
Array ( [id] => 11132450 [patent_doc_number] => 20160329425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/148612 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11456 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148612
Semiconductor device May 5, 2016 Issued
Array ( [id] => 12195545 [patent_doc_number] => 09899282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Robust high performance semiconductor package' [patent_app_type] => utility [patent_app_number] => 15/148144 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148144 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148144
Robust high performance semiconductor package May 5, 2016 Issued
Array ( [id] => 11898158 [patent_doc_number] => 09768099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'IC package with integrated inductor' [patent_app_type] => utility [patent_app_number] => 15/148248 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5413 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148248 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148248
IC package with integrated inductor May 5, 2016 Issued
Array ( [id] => 11904472 [patent_doc_number] => 09773913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance' [patent_app_type] => utility [patent_app_number] => 15/148341 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148341 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148341
Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance May 5, 2016 Issued
Array ( [id] => 12033733 [patent_doc_number] => 20170323832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 15/148274 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6554 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148274
Dummy MOL removal for performance enhancement May 5, 2016 Issued
Array ( [id] => 13485225 [patent_doc_number] => 20180294155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => PROCESS FOR OBTAINING SEMICONDUCTOR NANODEVICES WITH PATTERNED METAL-OXIDE THIN FILMS DEPOSITED ONTO A SUBSTRATE, AND SEMICONDUCTOR NANODEVICES THEREOF [patent_app_type] => utility [patent_app_number] => 15/572059 [patent_app_country] => US [patent_app_date] => 2016-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15572059 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/572059
PROCESS FOR OBTAINING SEMICONDUCTOR NANODEVICES WITH PATTERNED METAL-OXIDE THIN FILMS DEPOSITED ONTO A SUBSTRATE, AND SEMICONDUCTOR NANODEVICES THEREOF May 2, 2016 Abandoned
Array ( [id] => 12025113 [patent_doc_number] => 20170315212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SYSTEM AND METHOD FOR USE OF QUALITATIVE MODELING FOR SIGNAL ANALYSIS' [patent_app_type] => utility [patent_app_number] => 15/141818 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10011 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141818 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141818
System and method for use of qualitative modeling for signal analysis Apr 27, 2016 Issued
Array ( [id] => 11116408 [patent_doc_number] => 20160313382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'MODULAR POWER METERING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/140076 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3417 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15140076 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/140076
Modular power metering system Apr 26, 2016 Issued
Array ( [id] => 13499623 [patent_doc_number] => 20180301354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => METHOD FOR MANUFACTURING A CIRCUIT CARRIER [patent_app_type] => utility [patent_app_number] => 15/574040 [patent_app_country] => US [patent_app_date] => 2016-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/574040
METHOD FOR MANUFACTURING A CIRCUIT CARRIER Apr 25, 2016 Abandoned
Array ( [id] => 12005428 [patent_doc_number] => 20170309583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'METHOD FOR PROCESSING AN ELECTRONIC COMPONENT AND AN ELECTRONIC COMPONENT' [patent_app_type] => utility [patent_app_number] => 15/135586 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 21324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135586
Method for processing an electronic component and an electronic component Apr 21, 2016 Issued
Array ( [id] => 11118037 [patent_doc_number] => 20160315011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'WAFER PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 15/135172 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7728 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135172
Wafer processing method Apr 20, 2016 Issued
Array ( [id] => 11557641 [patent_doc_number] => 20170103887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'METHOD FOR FORMING EPITAXIAL LAYER' [patent_app_type] => utility [patent_app_number] => 15/134722 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1638 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134722 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134722
METHOD FOR FORMING EPITAXIAL LAYER Apr 20, 2016 Abandoned
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