Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10985104 [patent_doc_number] => 20160182049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'Push-Pull Driver, A Transmitter, A Receiver, A Transceiver, An Integrated Circuit, A Method for Generating a Signal at an Output' [patent_app_type] => utility [patent_app_number] => 14/861629 [patent_app_country] => US [patent_app_date] => 2015-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15030 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14861629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/861629
Push-pull driver, a transmitter, a receiver, a transceiver, an integrated circuit, a method for generating a signal at an output Sep 21, 2015 Issued
Array ( [id] => 10667656 [patent_doc_number] => 20160013801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'REFERENCE-FREQUENCY-INSENSITIVE PHASE LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 14/860262 [patent_app_country] => US [patent_app_date] => 2015-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4640 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860262 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/860262
Reference-frequency-insensitive phase locked loop Sep 20, 2015 Issued
Array ( [id] => 11496034 [patent_doc_number] => 20170070219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'ADJUSTABLE DELAY CIRCUIT FOR OPTIMIZING TIMING MARGIN' [patent_app_type] => utility [patent_app_number] => 14/848954 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7500 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848954 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/848954
Adjustable delay circuit for optimizing timing margin Sep 8, 2015 Issued
Array ( [id] => 11616242 [patent_doc_number] => 09654113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Control device for clock generation circuit, control method for clock generation circuit, and clock generation circuit' [patent_app_type] => utility [patent_app_number] => 14/849067 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15516 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849067
Control device for clock generation circuit, control method for clock generation circuit, and clock generation circuit Sep 8, 2015 Issued
Array ( [id] => 11933042 [patent_doc_number] => 09800051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Method and apparatus for controlling energy flow between dissimilar energy storage devices' [patent_app_type] => utility [patent_app_number] => 14/844742 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 10924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844742 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/844742
Method and apparatus for controlling energy flow between dissimilar energy storage devices Sep 2, 2015 Issued
Array ( [id] => 11922204 [patent_doc_number] => 09789773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Power conversion apparatus and power control method' [patent_app_type] => utility [patent_app_number] => 14/844542 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9872 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844542 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/844542
Power conversion apparatus and power control method Sep 2, 2015 Issued
Array ( [id] => 11565492 [patent_doc_number] => 09628092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning' [patent_app_type] => utility [patent_app_number] => 14/841473 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 16565 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841473 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/841473
Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning Aug 30, 2015 Issued
Array ( [id] => 11476310 [patent_doc_number] => 20170063093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'ZERO NET ENERGY DC DATACENTER POWER DISTRIBUTION ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/836189 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836189 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836189
Zero net energy DC datacenter power distribution architecture Aug 25, 2015 Issued
Array ( [id] => 14595801 [patent_doc_number] => 10351080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Arrangement for electrically connecting electrical elements to a central unit in a motor vehicle [patent_app_type] => utility [patent_app_number] => 14/833314 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2205 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833314 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833314
Arrangement for electrically connecting electrical elements to a central unit in a motor vehicle Aug 23, 2015 Issued
Array ( [id] => 10703120 [patent_doc_number] => 20160049267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'Remote Controlled Light Switch Cover Assembly' [patent_app_type] => utility [patent_app_number] => 14/825117 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5708 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/825117
Remote controlled light switch cover assembly Aug 11, 2015 Issued
Array ( [id] => 11418050 [patent_doc_number] => 09564884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-07 [patent_title] => 'Circuitry and method for measuring negative bias temperature instability (NBTI) and hot carrier injection (HCI) aging effects using edge sensitive sampling' [patent_app_type] => utility [patent_app_number] => 14/791444 [patent_app_country] => US [patent_app_date] => 2015-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791444
Circuitry and method for measuring negative bias temperature instability (NBTI) and hot carrier injection (HCI) aging effects using edge sensitive sampling Jul 3, 2015 Issued
Array ( [id] => 11418048 [patent_doc_number] => 09564883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-07 [patent_title] => 'Circuitry and method for timing speculation via toggling functional critical paths' [patent_app_type] => utility [patent_app_number] => 14/791443 [patent_app_country] => US [patent_app_date] => 2015-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791443 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791443
Circuitry and method for timing speculation via toggling functional critical paths Jul 3, 2015 Issued
Array ( [id] => 10440184 [patent_doc_number] => 20150325195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 14/790309 [patent_app_country] => US [patent_app_date] => 2015-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 25204 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14790309 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/790309
Semiconductor device Jul 1, 2015 Issued
Array ( [id] => 11807622 [patent_doc_number] => 09548728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Time signal generating circuit and time signal generating method' [patent_app_type] => utility [patent_app_number] => 14/788812 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3706 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/788812
Time signal generating circuit and time signal generating method Jun 30, 2015 Issued
Array ( [id] => 11484024 [patent_doc_number] => 09590592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Configurable capacitor arrays and switched capacitor circuits' [patent_app_type] => utility [patent_app_number] => 14/752052 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752052 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752052
Configurable capacitor arrays and switched capacitor circuits Jun 25, 2015 Issued
Array ( [id] => 10442330 [patent_doc_number] => 20150327342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'LIGHT SOURCE APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/746857 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 12012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14746857 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/746857
Light source apparatus Jun 22, 2015 Issued
Array ( [id] => 10985113 [patent_doc_number] => 20160182058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHOD FOR CLOCK CALIBRATION' [patent_app_type] => utility [patent_app_number] => 14/743174 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743174 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/743174
Method for clock calibration Jun 17, 2015 Issued
Array ( [id] => 11392332 [patent_doc_number] => 09553587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Data output circuit of a semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 14/737815 [patent_app_country] => US [patent_app_date] => 2015-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6143 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/737815
Data output circuit of a semiconductor apparatus Jun 11, 2015 Issued
Array ( [id] => 11222219 [patent_doc_number] => 09450569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-20 [patent_title] => 'Very low power real time clock' [patent_app_type] => utility [patent_app_number] => 14/731308 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731308 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731308
Very low power real time clock Jun 3, 2015 Issued
Array ( [id] => 11287246 [patent_doc_number] => 09503109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Apparatus and methods for synchronizing phase-locked loops' [patent_app_type] => utility [patent_app_number] => 14/726913 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726913 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726913
Apparatus and methods for synchronizing phase-locked loops May 31, 2015 Issued
Menu