Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8898683 [patent_doc_number] => 08478214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Multi-port distributed antenna' [patent_app_type] => utility [patent_app_number] => 13/543171 [patent_app_country] => US [patent_app_date] => 2012-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13543171 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/543171
Multi-port distributed antenna Jul 5, 2012 Issued
Array ( [id] => 8863832 [patent_doc_number] => 20130147535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'TUNABLE ACTIVE DIRECTIONAL COUPLERS' [patent_app_type] => utility [patent_app_number] => 13/526031 [patent_app_country] => US [patent_app_date] => 2012-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9848 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13526031 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/526031
Tunable active directional couplers Jun 17, 2012 Issued
Array ( [id] => 9189290 [patent_doc_number] => 20130328605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'Non-Overlapping Clock Generator' [patent_app_type] => utility [patent_app_number] => 13/493114 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493114 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/493114
Non-overlapping clock generator Jun 10, 2012 Issued
Array ( [id] => 9350906 [patent_doc_number] => 08669801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Analog delay cells for the power supply of an RFID tag' [patent_app_type] => utility [patent_app_number] => 13/490267 [patent_app_country] => US [patent_app_date] => 2012-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 43 [patent_no_of_words] => 7868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13490267 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/490267
Analog delay cells for the power supply of an RFID tag Jun 5, 2012 Issued
Array ( [id] => 9376640 [patent_doc_number] => 08680905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-25 [patent_title] => 'Digital PVT compensation for delay chain' [patent_app_type] => utility [patent_app_number] => 13/486670 [patent_app_country] => US [patent_app_date] => 2012-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13486670 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/486670
Digital PVT compensation for delay chain May 31, 2012 Issued
Array ( [id] => 12088335 [patent_doc_number] => 09842066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Integrated circuit comprising an IO buffer driver and method therefor' [patent_app_type] => utility [patent_app_number] => 14/398876 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5179 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14398876 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/398876
Integrated circuit comprising an IO buffer driver and method therefor May 30, 2012 Issued
Array ( [id] => 9087156 [patent_doc_number] => 08558587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Gate driver' [patent_app_type] => utility [patent_app_number] => 13/482384 [patent_app_country] => US [patent_app_date] => 2012-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4667 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13482384 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/482384
Gate driver May 28, 2012 Issued
Array ( [id] => 8995862 [patent_doc_number] => 08519752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Apparatus for reducing simultaneous switching noise' [patent_app_type] => utility [patent_app_number] => 13/477703 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2346 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477703 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477703
Apparatus for reducing simultaneous switching noise May 21, 2012 Issued
Array ( [id] => 9091887 [patent_doc_number] => 20130271198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'CLOCK GENERATION METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/476017 [patent_app_country] => US [patent_app_date] => 2012-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2621 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13476017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/476017
Clock generation method and system May 20, 2012 Issued
Array ( [id] => 9021238 [patent_doc_number] => 08531225 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-10 [patent_title] => 'Configurable critical path emulator' [patent_app_type] => utility [patent_app_number] => 13/474717 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 30712 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474717 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/474717
Configurable critical path emulator May 17, 2012 Issued
Array ( [id] => 9159314 [patent_doc_number] => 20130307591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'DEPLETION-MODE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/471832 [patent_app_country] => US [patent_app_date] => 2012-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13471832 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/471832
Depletion-mode circuit May 14, 2012 Issued
Array ( [id] => 8380134 [patent_doc_number] => 20120223757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'Method and Apparatus for Clock Calibration in a Clocked Digital Device' [patent_app_type] => utility [patent_app_number] => 13/471204 [patent_app_country] => US [patent_app_date] => 2012-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13471204 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/471204
Method and apparatus for clock calibration in a clocked digital device May 13, 2012 Issued
Array ( [id] => 9414512 [patent_doc_number] => 08698551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Semiconductor device including a circuit configured to hold an offset voltage' [patent_app_type] => utility [patent_app_number] => 13/468135 [patent_app_country] => US [patent_app_date] => 2012-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 55 [patent_no_of_words] => 25160 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13468135 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/468135
Semiconductor device including a circuit configured to hold an offset voltage May 9, 2012 Issued
Array ( [id] => 9167513 [patent_doc_number] => 08593196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Test circuit and methods for speed characterization' [patent_app_type] => utility [patent_app_number] => 13/459659 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9563 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459659 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/459659
Test circuit and methods for speed characterization Apr 29, 2012 Issued
Array ( [id] => 8463008 [patent_doc_number] => 20120268176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'CIRCUIT AND METHOD FOR GENERATING MULTIPHASE CLOCK SIGNALS AND CORRESPONDING INDICATION SIGNALS' [patent_app_type] => utility [patent_app_number] => 13/452118 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3332 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452118 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452118
Circuit and method for generating multiphase clock signals and corresponding indication signals Apr 19, 2012 Issued
Array ( [id] => 9047495 [patent_doc_number] => 08542049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-24 [patent_title] => 'Methods and delay circuits for generating a plurality of delays in delay lines' [patent_app_type] => utility [patent_app_number] => 13/450088 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 11239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450088 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450088
Methods and delay circuits for generating a plurality of delays in delay lines Apr 17, 2012 Issued
Array ( [id] => 8702196 [patent_doc_number] => 08395421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-12 [patent_title] => 'Configurable buffer circuits and methods' [patent_app_type] => utility [patent_app_number] => 13/446772 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/446772
Configurable buffer circuits and methods Apr 12, 2012 Issued
Array ( [id] => 8440044 [patent_doc_number] => 20120256660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'SOURCE DRIVER AND RECEIVER THEREOF' [patent_app_type] => utility [patent_app_number] => 13/441211 [patent_app_country] => US [patent_app_date] => 2012-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3141 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441211 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/441211
Source driver and receiver thereof Apr 5, 2012 Issued
Array ( [id] => 9065742 [patent_doc_number] => 20130257498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'Pulse Clock Generation Logic with Built-in Level Shifter and Programmable Rising Edge and Pulse Width' [patent_app_type] => utility [patent_app_number] => 13/433891 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5471 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13433891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/433891
Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width Mar 28, 2012 Issued
Array ( [id] => 8427329 [patent_doc_number] => 20120249205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'Semiconductor Device, a Method of Improving a Distortion of an Output Waveform, and an Electronic Apparatus' [patent_app_type] => utility [patent_app_number] => 13/432097 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6802 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432097 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432097
Semiconductor device, a method of improving a distortion of an output waveform, and an electronic apparatus Mar 27, 2012 Issued
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