Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8427332 [patent_doc_number] => 20120249207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'CLOCK SIGNAL GENERATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/431275 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7938 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431275 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431275
Clock signal generation circuit Mar 26, 2012 Issued
Array ( [id] => 8718487 [patent_doc_number] => 20130069703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL' [patent_app_type] => utility [patent_app_number] => 13/428155 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11291 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428155 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428155
Uniform-footprint programmable-skew multi-stage delay cell Mar 22, 2012 Issued
Array ( [id] => 8604358 [patent_doc_number] => 20130009670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'SIGNAL OPERATING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/426616 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5783 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13426616 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/426616
Signal operating circuit Mar 21, 2012 Issued
Array ( [id] => 8451258 [patent_doc_number] => 20120262204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'DRIVER CIRCUIT HAVING AN INSULATED GATE FIELD EFFECT TRANSISTOR FOR PROVIDING POWER' [patent_app_type] => utility [patent_app_number] => 13/421091 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4098 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421091 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421091
DRIVER CIRCUIT HAVING AN INSULATED GATE FIELD EFFECT TRANSISTOR FOR PROVIDING POWER Mar 14, 2012 Abandoned
Array ( [id] => 8871347 [patent_doc_number] => 08466726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Duty cycle correction systems and methods' [patent_app_type] => utility [patent_app_number] => 13/420459 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420459 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/420459
Duty cycle correction systems and methods Mar 13, 2012 Issued
Array ( [id] => 8676343 [patent_doc_number] => 08384460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Techniques for phase adjustment' [patent_app_type] => utility [patent_app_number] => 13/420349 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12688 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420349 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/420349
Techniques for phase adjustment Mar 13, 2012 Issued
Array ( [id] => 8593974 [patent_doc_number] => 08351853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Configurable filter using a transmission line as a delay line' [patent_app_type] => utility [patent_app_number] => 13/412446 [patent_app_country] => US [patent_app_date] => 2012-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13412446 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/412446
Configurable filter using a transmission line as a delay line Mar 4, 2012 Issued
Array ( [id] => 8987545 [patent_doc_number] => 20130214826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'FULLY DIGITAL METHOD FOR GENERATING SUB CLOCK DIVISION AND CLOCK WAVES' [patent_app_type] => utility [patent_app_number] => 13/402264 [patent_app_country] => US [patent_app_date] => 2012-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2057 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13402264 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/402264
Fully digital method for generating sub clock division and clock waves Feb 21, 2012 Issued
Array ( [id] => 8237963 [patent_doc_number] => 20120146702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'PHASE MIXER WITH ADJUSTABLE LOAD-TO-DRIVE RATIO' [patent_app_type] => utility [patent_app_number] => 13/397511 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3911 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397511 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397511
Phase mixer with adjustable load-to-drive ratio Feb 14, 2012 Issued
Array ( [id] => 8995860 [patent_doc_number] => 08519750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Semiconductor switching device drive circuit' [patent_app_type] => utility [patent_app_number] => 13/371858 [patent_app_country] => US [patent_app_date] => 2012-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 12771 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13371858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/371858
Semiconductor switching device drive circuit Feb 12, 2012 Issued
Array ( [id] => 9228082 [patent_doc_number] => 08633753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Clock distribution system and method for a multi-bit latch' [patent_app_type] => utility [patent_app_number] => 13/369698 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2235 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369698
Clock distribution system and method for a multi-bit latch Feb 8, 2012 Issued
Array ( [id] => 9179114 [patent_doc_number] => 20130321099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'FILTER FOR A MAGNETRON POWER SUPPLY LEAD' [patent_app_type] => utility [patent_app_number] => 13/985008 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3038 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13985008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/985008
Filter for a magnetron power supply lead Feb 8, 2012 Issued
Array ( [id] => 9376643 [patent_doc_number] => 08680908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'On-chip coarse delay calibration' [patent_app_type] => utility [patent_app_number] => 13/368906 [patent_app_country] => US [patent_app_date] => 2012-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3550 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13368906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/368906
On-chip coarse delay calibration Feb 7, 2012 Issued
Array ( [id] => 9250815 [patent_doc_number] => 08614598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Output circuit, system including output circuit, and method of controlling output circuit' [patent_app_type] => utility [patent_app_number] => 13/357469 [patent_app_country] => US [patent_app_date] => 2012-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6153 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13357469 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357469
Output circuit, system including output circuit, and method of controlling output circuit Jan 23, 2012 Issued
Array ( [id] => 8937900 [patent_doc_number] => 20130187697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-25 [patent_title] => 'MULTI-LEVEL HIGH VOLTAGE PULSER INTEGRATED CIRCUIT USING LOW VOLTAGE MOSFETS' [patent_app_type] => utility [patent_app_number] => 13/355749 [patent_app_country] => US [patent_app_date] => 2012-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2697 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13355749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/355749
Multi-level high voltage pulser integrated circuit using low voltage MOSFETs Jan 22, 2012 Issued
Array ( [id] => 8657539 [patent_doc_number] => 20130038369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'Delay Cell and Digitally Controlled Oscillator' [patent_app_type] => utility [patent_app_number] => 13/352350 [patent_app_country] => US [patent_app_date] => 2012-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13352350 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/352350
Delay cell and digitally controlled oscillator Jan 17, 2012 Issued
Array ( [id] => 9778899 [patent_doc_number] => 08854109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Method for controlling two electrically series-connected reverse conductive IGBTs of a half bridge' [patent_app_type] => utility [patent_app_number] => 13/984790 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 5460 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984790 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/984790
Method for controlling two electrically series-connected reverse conductive IGBTs of a half bridge Jan 12, 2012 Issued
Array ( [id] => 9345841 [patent_doc_number] => 08664992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Duty cycle controlling circuit, duty cycle adjusting cell, and dutycycle detecting circuit' [patent_app_type] => utility [patent_app_number] => 13/342217 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4208 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342217 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342217
Duty cycle controlling circuit, duty cycle adjusting cell, and dutycycle detecting circuit Jan 2, 2012 Issued
Array ( [id] => 8969455 [patent_doc_number] => 08508274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Duty correction circuit' [patent_app_type] => utility [patent_app_number] => 13/341436 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9485 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13341436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/341436
Duty correction circuit Dec 29, 2011 Issued
Array ( [id] => 9113894 [patent_doc_number] => 08570075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Gate driver with digital ground' [patent_app_type] => utility [patent_app_number] => 13/339433 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2076 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339433 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/339433
Gate driver with digital ground Dec 28, 2011 Issued
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