Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9246192 [patent_doc_number] => 08610477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Wideband analog phase shifter' [patent_app_type] => utility [patent_app_number] => 13/068123 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13068123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/068123
Wideband analog phase shifter May 2, 2011 Issued
Array ( [id] => 8029685 [patent_doc_number] => 08143928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Duty cycle correction systems and methods' [patent_app_type] => utility [patent_app_number] => 13/098154 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/143/08143928.pdf [firstpage_image] =>[orig_patent_app_number] => 13098154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/098154
Duty cycle correction systems and methods Apr 28, 2011 Issued
Array ( [id] => 6059446 [patent_doc_number] => 20110199129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'Line Driver with Reduced Dependency on Process, Voltage, and Temperature' [patent_app_type] => utility [patent_app_number] => 13/095688 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20110199129.pdf [firstpage_image] =>[orig_patent_app_number] => 13095688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/095688
Line driver with reduced dependency on process, voltage, and temperature Apr 26, 2011 Issued
Array ( [id] => 8262399 [patent_doc_number] => 20120161828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Clock Generating Circuit and Clock Generating Method' [patent_app_type] => utility [patent_app_number] => 13/093396 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093396 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093396
Clock generating circuit and clock generating method Apr 24, 2011 Issued
Array ( [id] => 8921718 [patent_doc_number] => 08487659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Comparator with adaptive timing' [patent_app_type] => utility [patent_app_number] => 13/092465 [patent_app_country] => US [patent_app_date] => 2011-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4106 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13092465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092465
Comparator with adaptive timing Apr 21, 2011 Issued
Array ( [id] => 7773745 [patent_doc_number] => 20120038391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'TRANSISTOR MODULE AND TRANSISTOR DRIVING MODULE' [patent_app_type] => utility [patent_app_number] => 13/092142 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4099 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20120038391.pdf [firstpage_image] =>[orig_patent_app_number] => 13092142 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/092142
Transistor module and transistor driving module Apr 20, 2011 Issued
Array ( [id] => 8630739 [patent_doc_number] => 08362818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Clock adjustment circuit, shift detection circuit of duty ratio, imaging device and clock adjustment method' [patent_app_type] => utility [patent_app_number] => 13/090467 [patent_app_country] => US [patent_app_date] => 2011-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 11226 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13090467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/090467
Clock adjustment circuit, shift detection circuit of duty ratio, imaging device and clock adjustment method Apr 19, 2011 Issued
Array ( [id] => 7497316 [patent_doc_number] => 20110260756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Buffer Circuit for a Capacitive Load of High Value' [patent_app_type] => utility [patent_app_number] => 13/090687 [patent_app_country] => US [patent_app_date] => 2011-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4919 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260756.pdf [firstpage_image] =>[orig_patent_app_number] => 13090687 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/090687
Buffer circuit for a capacitive load of high value Apr 19, 2011 Issued
Array ( [id] => 7584642 [patent_doc_number] => 20110279152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'LOAD DRIVING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/090488 [patent_app_country] => US [patent_app_date] => 2011-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15214 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20110279152.pdf [firstpage_image] =>[orig_patent_app_number] => 13090488 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/090488
Load driving device Apr 19, 2011 Issued
Array ( [id] => 8621953 [patent_doc_number] => 08354869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-15 [patent_title] => 'Systems and methods for controlling power supply current using clock gating' [patent_app_type] => utility [patent_app_number] => 13/090600 [patent_app_country] => US [patent_app_date] => 2011-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13090600 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/090600
Systems and methods for controlling power supply current using clock gating Apr 19, 2011 Issued
Array ( [id] => 8178754 [patent_doc_number] => 08179182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Method and apparatus for clock calibration in a clocked digital device' [patent_app_type] => utility [patent_app_number] => 13/088783 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 12405 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/179/08179182.pdf [firstpage_image] =>[orig_patent_app_number] => 13088783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088783
Method and apparatus for clock calibration in a clocked digital device Apr 17, 2011 Issued
Array ( [id] => 8451262 [patent_doc_number] => 20120262209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'Multi-Phase Clock Generator and Data Transmission Lines' [patent_app_type] => utility [patent_app_number] => 13/089160 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089160 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089160
Multi-phase clock generator and data transmission lines Apr 17, 2011 Issued
Array ( [id] => 8676347 [patent_doc_number] => 08384464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Low jitter clock interpolator' [patent_app_type] => utility [patent_app_number] => 13/084453 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4177 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13084453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/084453
Low jitter clock interpolator Apr 10, 2011 Issued
Array ( [id] => 7480784 [patent_doc_number] => 20110248749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/081957 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3714 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248749.pdf [firstpage_image] =>[orig_patent_app_number] => 13081957 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/081957
Semiconductor device Apr 6, 2011 Issued
Array ( [id] => 8556030 [patent_doc_number] => 08330505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Protection circuit for driving capacitive loads' [patent_app_type] => utility [patent_app_number] => 13/076814 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4150 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13076814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/076814
Protection circuit for driving capacitive loads Mar 30, 2011 Issued
Array ( [id] => 8630735 [patent_doc_number] => 08362813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Re-driver with pre-emphasis injected through a transformer and tuned by an L-C tank' [patent_app_type] => utility [patent_app_number] => 13/071448 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13071448 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/071448
Re-driver with pre-emphasis injected through a transformer and tuned by an L-C tank Mar 23, 2011 Issued
Array ( [id] => 8897420 [patent_doc_number] => 08476945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Phase profile generator' [patent_app_type] => utility [patent_app_number] => 13/069653 [patent_app_country] => US [patent_app_date] => 2011-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7381 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13069653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/069653
Phase profile generator Mar 22, 2011 Issued
Array ( [id] => 6099735 [patent_doc_number] => 20110163790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/052099 [patent_app_country] => US [patent_app_date] => 2011-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7929 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20110163790.pdf [firstpage_image] =>[orig_patent_app_number] => 13052099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/052099
Signal processing circuit and signal processing method Mar 19, 2011 Issued
Array ( [id] => 8847025 [patent_doc_number] => 08456212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Duty correcting circuit, delay-locked loop circuit including the circuit, and method of correcting duty' [patent_app_type] => utility [patent_app_number] => 13/050652 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13050652 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050652
Duty correcting circuit, delay-locked loop circuit including the circuit, and method of correcting duty Mar 16, 2011 Issued
Array ( [id] => 7698968 [patent_doc_number] => 20110227622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'BUFFER CIRCUIT AND DUTY CYCLE CORRECTION METHOD USING SAME' [patent_app_type] => utility [patent_app_number] => 13/050414 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6905 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20110227622.pdf [firstpage_image] =>[orig_patent_app_number] => 13050414 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050414
Buffer circuit and duty cycle correction method using same Mar 16, 2011 Issued
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