An T. Luu

Array ( [id] => 8167471 [patent_doc_number] => 20120105139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/982731 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20120105139.pdf [firstpage_image] =>[orig_patent_app_number] => 12982731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8190741 [patent_doc_number] => 08183904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Control system for a phase generator and corresponding control method' [patent_app_type] => utility [patent_app_number] => 12/980486 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5167 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183904.pdf [firstpage_image] =>[orig_patent_app_number] => 12980486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8739733 [patent_doc_number] => 08411514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Multi-chip package including output enable signal generation circuit and data output control method thereof' [patent_app_type] => utility [patent_app_number] => 12/981453 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3393 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8422497 [patent_doc_number] => 08278986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Trimming of a pseudo-closed loop programmable delay line' [patent_app_type] => utility [patent_app_number] => 12/977093 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8048 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12977093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6099730 [patent_doc_number] => 20110163785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'SIMPLE INTERLEAVED PHASE SHIFT CLOCK SYNCHRONIZATION FOR MASTER/SLAVE SCHEME' [patent_app_type] => utility [patent_app_number] => 12/977662 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20110163785.pdf [firstpage_image] =>[orig_patent_app_number] => 12977662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8329378 [patent_doc_number] => 08237482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Circuit and method for generating a clock signal' [patent_app_type] => utility [patent_app_number] => 12/975129 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5205 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12975129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8249691 [patent_doc_number] => 20120154011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'METHOD AND APPARATUS FOR PHASE SELECTION ACCELERATION' [patent_app_type] => utility [patent_app_number] => 12/974501 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2410 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20120154011.pdf [firstpage_image] =>[orig_patent_app_number] => 12974501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6155104 [patent_doc_number] => 20110156764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'METHOD FOR CALIBRATING AND CONTROLLING SIGNAL SLEW RATE, AND OUTPUT STAGE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/971617 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3298 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156764.pdf [firstpage_image] =>[orig_patent_app_number] => 12971617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8167447 [patent_doc_number] => 20120105122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DUTY CYCLE CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/970931 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5860 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20120105122.pdf [firstpage_image] =>[orig_patent_app_number] => 12970931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8237964 [patent_doc_number] => 20120146701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'CLOCK SYSTEM AND METHOD FOR COMPENSATING TIMING INFORMATION OF CLOCK SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/965917 [patent_app_country] => US [patent_app_date] => 2010-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4415 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12965917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8193782 [patent_doc_number] => 20120119809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'CLOCK CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/965372 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3185 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119809.pdf [firstpage_image] =>[orig_patent_app_number] => 12965372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5964648 [patent_doc_number] => 20110148506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'INTEGRATION OF MOSFETS IN A SOURCE-DOWN CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 12/964527 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20110148506.pdf [firstpage_image] =>[orig_patent_app_number] => 12964527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10508978 [patent_doc_number] => 09236856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Apparatus for controlling slew rate' [patent_app_type] => utility [patent_app_number] => 12/964412 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3385 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12964412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6209145 [patent_doc_number] => 20110133792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'BUFFER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/963194 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 11703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133792.pdf [firstpage_image] =>[orig_patent_app_number] => 12963194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8376031 [patent_doc_number] => 08258821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Multi-voltage input buffer' [patent_app_type] => utility [patent_app_number] => 12/959142 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12959142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6138531 [patent_doc_number] => 20110128061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'Phase Generating Apparatus and Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/957524 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7304 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128061.pdf [firstpage_image] =>[orig_patent_app_number] => 12957524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8921723 [patent_doc_number] => 08487664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'System and method for driving a switch' [patent_app_type] => utility [patent_app_number] => 12/956852 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7054 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12956852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8534123 [patent_doc_number] => 08310281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'System and method for driving a cascode switch' [patent_app_type] => utility [patent_app_number] => 12/956696 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12956696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6021965 [patent_doc_number] => 20110050291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Method and apparatus for adjusting driver output current and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 12/926229 [patent_app_country] => US [patent_app_date] => 2010-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6487 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20110050291.pdf [firstpage_image] =>[orig_patent_app_number] => 12926229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8785363 [patent_doc_number] => 08432210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Fine-grained clock skew tuning in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/938172 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6165 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12938172 [rel_patent_id] =>[rel_patent_doc_number] =>)