Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8271088 [patent_doc_number] => 08212601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Method and apparatus for providing system clock failover' [patent_app_type] => utility [patent_app_number] => 12/915464 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12915464 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/915464
Method and apparatus for providing system clock failover Oct 28, 2010 Issued
Array ( [id] => 8306578 [patent_doc_number] => 08228113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Power semiconductor module and method for operating a power semiconductor module' [patent_app_type] => utility [patent_app_number] => 12/914301 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10486 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12914301 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914301
Power semiconductor module and method for operating a power semiconductor module Oct 27, 2010 Issued
Array ( [id] => 8233480 [patent_doc_number] => 08198930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Reducing power-supply-induced jitter in a clock-distribution circuit' [patent_app_type] => utility [patent_app_number] => 12/913754 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 8140 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/198/08198930.pdf [firstpage_image] =>[orig_patent_app_number] => 12913754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913754
Reducing power-supply-induced jitter in a clock-distribution circuit Oct 26, 2010 Issued
Array ( [id] => 7667332 [patent_doc_number] => 20110316601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'Method and Device for Delaying Activation Timing of Output Device' [patent_app_type] => utility [patent_app_number] => 12/912759 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3688 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12912759 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/912759
Method and device for delaying activation timing of output device Oct 26, 2010 Issued
Array ( [id] => 8166195 [patent_doc_number] => 08174294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-08 [patent_title] => 'Configurable buffer circuits and methods' [patent_app_type] => utility [patent_app_number] => 12/910177 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174294.pdf [firstpage_image] =>[orig_patent_app_number] => 12910177 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/910177
Configurable buffer circuits and methods Oct 21, 2010 Issued
Array ( [id] => 6036951 [patent_doc_number] => 20110090000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SIGNAL TRANSMISSION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/908563 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4675 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20110090000.pdf [firstpage_image] =>[orig_patent_app_number] => 12908563 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/908563
SIGNAL TRANSMISSION CIRCUIT Oct 19, 2010 Abandoned
Array ( [id] => 6036931 [patent_doc_number] => 20110089980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'CAPACITIVE LOAD DRIVER' [patent_app_type] => utility [patent_app_number] => 12/907307 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3143 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089980.pdf [firstpage_image] =>[orig_patent_app_number] => 12907307 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/907307
Capacitive load driver Oct 18, 2010 Issued
Array ( [id] => 6193641 [patent_doc_number] => 20110025395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'SYSTEM AND METHOD FOR COMPENSATING PULSE GENERATOR FOR PROCESS AND TEMPERATURE VARIATIONS' [patent_app_type] => utility [patent_app_number] => 12/904977 [patent_app_country] => US [patent_app_date] => 2010-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4688 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20110025395.pdf [firstpage_image] =>[orig_patent_app_number] => 12904977 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/904977
System and method for compensating pulse generator for process and temperature variations Oct 13, 2010 Issued
Array ( [id] => 8956787 [patent_doc_number] => 08502569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Architecture for operating resonant clock network in conventional mode' [patent_app_type] => utility [patent_app_number] => 12/903174 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5079 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903174 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903174
Architecture for operating resonant clock network in conventional mode Oct 11, 2010 Issued
Array ( [id] => 8123859 [patent_doc_number] => 20120086476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'Fast and accurate current driver with zero standby current and features for boost and temperature compensation for MRAM write circuit' [patent_app_type] => utility [patent_app_number] => 12/925004 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2843 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20120086476.pdf [firstpage_image] =>[orig_patent_app_number] => 12925004 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/925004
Fast and accurate current driver with zero standby current and features for boost and temperature compensation for MRAM write circuit Oct 11, 2010 Issued
Array ( [id] => 8643460 [patent_doc_number] => 08368450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Architecture for adjusting natural frequency in resonant clock distribution networks' [patent_app_type] => utility [patent_app_number] => 12/903166 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4743 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903166 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903166
Architecture for adjusting natural frequency in resonant clock distribution networks Oct 11, 2010 Issued
Array ( [id] => 8630734 [patent_doc_number] => 08362811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Architecture for single-stepping in resonant clock distribution networks' [patent_app_type] => utility [patent_app_number] => 12/903172 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5378 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903172
Architecture for single-stepping in resonant clock distribution networks Oct 11, 2010 Issued
Array ( [id] => 6121755 [patent_doc_number] => 20110084775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAMETER VARIATIONS IN CONVENTIONAL CLOCK DISTRIBUTION NETWORKS' [patent_app_type] => utility [patent_app_number] => 12/903188 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5338 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084775.pdf [firstpage_image] =>[orig_patent_app_number] => 12903188 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903188
Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks Oct 11, 2010 Issued
Array ( [id] => 8714048 [patent_doc_number] => 08400192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Architecture for frequency-scaled operation in resonant clock distribution networks' [patent_app_type] => utility [patent_app_number] => 12/903168 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6020 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903168 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903168
Architecture for frequency-scaled operation in resonant clock distribution networks Oct 11, 2010 Issued
Array ( [id] => 8123881 [patent_doc_number] => 20120086491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'INTEGRATED JITTER COMPLIANT CLOCK SIGNAL GENERATION' [patent_app_type] => utility [patent_app_number] => 12/900424 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4686 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20120086491.pdf [firstpage_image] =>[orig_patent_app_number] => 12900424 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/900424
Integrated jitter compliant clock signal generation Oct 6, 2010 Issued
Array ( [id] => 8306575 [patent_doc_number] => 08228107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Clock signal balancing circuit and method for balancing clock signal in IC layout' [patent_app_type] => utility [patent_app_number] => 12/897795 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4263 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12897795 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/897795
Clock signal balancing circuit and method for balancing clock signal in IC layout Oct 4, 2010 Issued
Array ( [id] => 8091111 [patent_doc_number] => 20120081164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'Timing circuit and method of generating an output timing signal' [patent_app_type] => utility [patent_app_number] => 12/923724 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6604 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20120081164.pdf [firstpage_image] =>[orig_patent_app_number] => 12923724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923724
Timing circuit and method of generating an output timing signal Oct 4, 2010 Issued
Array ( [id] => 8403657 [patent_doc_number] => 20120235712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'HIGH VOLTAGE SEMICONDUCTOR DEVICE AND DRIVING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/256222 [patent_app_country] => US [patent_app_date] => 2010-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13841 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13256222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/256222
High voltage semiconductor device and driving circuit Sep 28, 2010 Issued
Array ( [id] => 8376020 [patent_doc_number] => 08258825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Spread spectrum circuit' [patent_app_type] => utility [patent_app_number] => 12/892571 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1800 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12892571 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/892571
Spread spectrum circuit Sep 27, 2010 Issued
Array ( [id] => 8153543 [patent_doc_number] => 08169247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Multiphase clock generation circuit' [patent_app_type] => utility [patent_app_number] => 12/888207 [patent_app_country] => US [patent_app_date] => 2010-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7122 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169247.pdf [firstpage_image] =>[orig_patent_app_number] => 12888207 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/888207
Multiphase clock generation circuit Sep 21, 2010 Issued
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