Search

An T. Luu

Examiner (ID: 5797, Phone: (571)272-1746 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2502, 2816, 2842
Total Applications
2105
Issued Applications
1967
Pending Applications
23
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6324436 [patent_doc_number] => 20100244906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'CURRENT DRIVE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/716272 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2860 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244906.pdf [firstpage_image] =>[orig_patent_app_number] => 12716272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716272
Current drive circuit Mar 2, 2010 Issued
Array ( [id] => 6512256 [patent_doc_number] => 20100219871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'GENERATION OF A LOW JITTER CLOCK SIGNAL' [patent_app_type] => utility [patent_app_number] => 12/714150 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5592 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219871.pdf [firstpage_image] =>[orig_patent_app_number] => 12714150 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714150
Generation of a low jitter clock signal Feb 25, 2010 Issued
Array ( [id] => 8572524 [patent_doc_number] => 08339174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Apparatus, circuit and method for automatic phase-shifting pulse width modulated signal generation' [patent_app_type] => utility [patent_app_number] => 12/712930 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12712930 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712930
Apparatus, circuit and method for automatic phase-shifting pulse width modulated signal generation Feb 24, 2010 Issued
Array ( [id] => 7535913 [patent_doc_number] => 08049547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Semiconductor integrated circuit and signal adjusting method' [patent_app_type] => utility [patent_app_number] => 12/712672 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 12862 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/049/08049547.pdf [firstpage_image] =>[orig_patent_app_number] => 12712672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712672
Semiconductor integrated circuit and signal adjusting method Feb 24, 2010 Issued
Array ( [id] => 6475186 [patent_doc_number] => 20100207675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/656816 [patent_app_country] => US [patent_app_date] => 2010-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207675.pdf [firstpage_image] =>[orig_patent_app_number] => 12656816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656816
Semiconductor device Feb 16, 2010 Issued
Array ( [id] => 6475197 [patent_doc_number] => 20100207676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'SIGNAL CONVERTING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/703985 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2720 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207676.pdf [firstpage_image] =>[orig_patent_app_number] => 12703985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703985
SIGNAL CONVERTING DEVICE Feb 10, 2010 Abandoned
Array ( [id] => 6162219 [patent_doc_number] => 20110193598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'EFFICIENT RETIMER FOR CLOCK DIVIDERS' [patent_app_type] => utility [patent_app_number] => 12/704192 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3289 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193598.pdf [firstpage_image] =>[orig_patent_app_number] => 12704192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704192
EFFICIENT RETIMER FOR CLOCK DIVIDERS Feb 10, 2010 Abandoned
Array ( [id] => 7528112 [patent_doc_number] => 08044711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-25 [patent_title] => 'Clock signal noise shaping' [patent_app_type] => utility [patent_app_number] => 12/704150 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2620 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/044/08044711.pdf [firstpage_image] =>[orig_patent_app_number] => 12704150 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704150
Clock signal noise shaping Feb 10, 2010 Issued
Array ( [id] => 6619130 [patent_doc_number] => 20100225366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'SIGNAL GENERATOR WITH OUTPUT FREQUENCY GREATER THAN THE OSCILLATOR FREQUENCY' [patent_app_type] => utility [patent_app_number] => 12/703022 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4883 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20100225366.pdf [firstpage_image] =>[orig_patent_app_number] => 12703022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703022
Signal generator with output frequency greater than the oscillator frequency Feb 8, 2010 Issued
Array ( [id] => 6554525 [patent_doc_number] => 20100127762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'OPEN-DRAIN OUTPUT BUFFER FOR SINGLE-VOLTAGE-SUPPLY CMOS' [patent_app_type] => utility [patent_app_number] => 12/699239 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5298 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20100127762.pdf [firstpage_image] =>[orig_patent_app_number] => 12699239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699239
Open-drain output buffer for single-voltage-supply CMOS Feb 2, 2010 Issued
Array ( [id] => 4473196 [patent_doc_number] => 07944264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Variable delay circuit, variable delay circuit controlling method, and input/output circuit' [patent_app_type] => utility [patent_app_number] => 12/656239 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944264.pdf [firstpage_image] =>[orig_patent_app_number] => 12656239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656239
Variable delay circuit, variable delay circuit controlling method, and input/output circuit Jan 20, 2010 Issued
Array ( [id] => 6522186 [patent_doc_number] => 20100123489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'PROCESS INSENSITIVE DELAY LINE' [patent_app_type] => utility [patent_app_number] => 12/690124 [patent_app_country] => US [patent_app_date] => 2010-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123489.pdf [firstpage_image] =>[orig_patent_app_number] => 12690124 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690124
Process insensitive delay line Jan 19, 2010 Issued
Array ( [id] => 6426286 [patent_doc_number] => 20100102869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'Apparatus and Method for Generating a Clock Signal' [patent_app_type] => utility [patent_app_number] => 12/650125 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14210 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20100102869.pdf [firstpage_image] =>[orig_patent_app_number] => 12650125 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650125
Apparatus and method for generating a clock signal Dec 29, 2009 Issued
Array ( [id] => 4601160 [patent_doc_number] => 07977996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Pulse generator with precision edge placement' [patent_app_type] => utility [patent_app_number] => 12/645563 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/977/07977996.pdf [firstpage_image] =>[orig_patent_app_number] => 12645563 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645563
Pulse generator with precision edge placement Dec 22, 2009 Issued
Array ( [id] => 6193630 [patent_doc_number] => 20110025384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/646608 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5154 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20110025384.pdf [firstpage_image] =>[orig_patent_app_number] => 12646608 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/646608
Device for generating clock in semiconductor integrated circuit Dec 22, 2009 Issued
Array ( [id] => 9168903 [patent_doc_number] => 08594591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Transmission system' [patent_app_type] => utility [patent_app_number] => 13/514008 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3710 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13514008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/514008
Transmission system Dec 16, 2009 Issued
Array ( [id] => 6076225 [patent_doc_number] => 20110140752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'Adaptive Clock Generators, Systems, and Methods' [patent_app_type] => utility [patent_app_number] => 12/637321 [patent_app_country] => US [patent_app_date] => 2009-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7445 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140752.pdf [firstpage_image] =>[orig_patent_app_number] => 12637321 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/637321
Adaptive clock generators, systems, and methods Dec 13, 2009 Issued
Array ( [id] => 6370183 [patent_doc_number] => 20100080325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Method and System for Independent I and Q Loop Amplitude Control for Quadrature Generators' [patent_app_type] => utility [patent_app_number] => 12/632184 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8797 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080325.pdf [firstpage_image] =>[orig_patent_app_number] => 12632184 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/632184
Method and system for independent I and Q loop amplitude control for quadrature generators Dec 6, 2009 Issued
Array ( [id] => 6209157 [patent_doc_number] => 20110133804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'CLOCK INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/631661 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 6988 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133804.pdf [firstpage_image] =>[orig_patent_app_number] => 12631661 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631661
Clock integrated circuit Dec 3, 2009 Issued
Array ( [id] => 4597569 [patent_doc_number] => 07982517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Delay line' [patent_app_type] => utility [patent_app_number] => 12/627415 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9578 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/982/07982517.pdf [firstpage_image] =>[orig_patent_app_number] => 12627415 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/627415
Delay line Nov 29, 2009 Issued
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